Enabling region 1 (DRAE-1) of EDMA on OMAP L138E for DSP applications.

Kartik Gurlhosur

Other Parts Discussed in Thread: OMAP-L138

I am trying to enable EDMA region 1 by writing in the DRAE1 register located at the address 0x01C00000+0x340+0x8, the value I am writing is 0xFFFFFFFF and when I read it back I get 0x0. I did the same with DRAE0 and the value I read back is correct (0xFFFFFFFF). Is there anything else I need to do before I enable DRAE1 ? I am referring to OMAP-L138.pdf & omap-l138.pdf.

I printed the Revision ID Register (REVID) which is 0x40019b00 and also the EDMA3CC Configuration Register (CCCFG) which is 0x213344 for EDMA_3_0 but 0x203344 for EDMA_3_1. My datasheet has the value R-4001 5300h for REVID register and looking at the CCCFG register the values appear incorrect.

over 9 years ago

0 Sivaraj Kuppuraj over 9 years ago

TI__Mastermind 35645 points

Hi,

Thanks for your post.

Usually, writes to the shadow region memory maps are governed by region access enable registers (DRAE/QRAE). If the appropriate channels are not enabled in these registers, read/write access to the shadow region memorymap will not be enabled.

When working with shadow region completion interrupts, ensure that the DMA region access enable registers (DRAE) for every region are set in a mutually exclusive way. If there is an overlap in the allocated channels and transfer completion codes (setting of interrupt pending register bits) in the region resource allocation, it results in multiple shadow regions completion interrupts. For example, if DRAE0.E0 and DRAE1.E0 are both set, then on completion of a transfer that returns a TCC = 0 will generate both shadow region 0 and 1 completion interrupts.

Thanks & regards,

Sivaraj K

-------------------------------------------------------------------------------------------------------

Please click the Verify Answer button on this post if it answers your question.

--------------------------------------------------------------------------------------------------------

0 Kartik Gurlhosur over 9 years ago in reply to Sivaraj Kuppuraj

Prodigy 190 points

I am not able to get the interrupts from DSP side. Are there any additional settings like GPIO configuration to route the interrupts to DSP? Any thing in Power module? My EDMA CCCFG is 0x213344 & PID is 0x40019b00. Does this EDMA support Region1 and routing of interrupts to DSP core?

0 Sivaraj Kuppuraj over 9 years ago in reply to Kartik Gurlhosur

TI__Mastermind 35645 points

Hi,

Thanks for your update.

It is not required to have additional configuration for GPIO or PSC to trigger an interrupt from DSP side. It's all depends on the DSP interrupt controller where the interrupt source from CPU/master peripherals mapped to 128 device events would combine to any of the available 12 prioritized CPU NMI's which are user programmable in the ISR. Kindly refer Table 6-8 from the datasheet below:

http://www.ti.com/lit/ds/symlink/omap-l138.pdf

In general, the EDMA3CC has interrupt evaluate registers (IEVAL) in each shadow region. These registers are the only registers in the DMA channel shadow region memory map which are not affected by the settings for the DMA region access enable registers (DRAE). A write of 1 to the EVAL bit in these registers associated with a particular shadow region would result in asserting the associated region interrupt, if any interrupt enabled (via IER) is still pending (IPR). By this way, through this register, we could assure that the interrupts are not missed by the CPU or the EDMA3 master associated with the shadow region.