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edma sync type and interrupt problem

Hello, I’m using edma, but I’m confused with it, as the SPRU234C documented, thee are four sync type transfer, that is

Element-Synchronized Transfer: An element-synchronized transfer

submits a transfer request (TR) for a single element when a synchronization

event is received. The EDMA channel controller updates the source

address, destination address, element count, and frame count after each

TR.

_ Frame-Synchronized Transfer: A frame-synchronized transfer submits

a transfer request (TR) for a single frame of element count elements when

a synchronization event is received. The EDMA channel controller

updates the source address, destination address, and frame count after

each TR. Elements and frames are spaced by a programmable index.

 

Array-Synchronized Transfer: An array-synchronized transfer submits

a transfer request (TR) for a single array of element count elements when

a synchronization event is received. The EDMA channel controller

updates the source address, destination address, and array count after

each TR. Elements are always contiguous and frames are spaced by a

programmable index.

_ Block-Synchronized Transfer: A block-synchronized transfer submits a

transfer request (TR) for an array count arrays of element count elements

when a synchronization event is received. The EDMA channel controller

does not perform any address or count updates. Elements are always

contiguous and frames are spaced by a programmable index.

 

But from the EDMA Channel Options Parameter (OPT), I found the FS field controls the sync type, the description as follow:

as above,if I set FS=0, I can’t decide what sync type (Element-Synchronized or Array-Synchronized)it is , and I don’t know how to configure Block-Synchronized Transfer,.

Another question, in my opinion, I think if a sync event is received by the Channel controller, a TR will submit to the transfer controller , after that the channel will update the parameter when the sync event receive ,after the sync event received until the PaRAM channel entry exhaust, an transfer completion interrupt will interrupt, is this opinion right or wrong?

can someone help me , waiting for your help, thank you.

  • Hi,

    Thanks for your post.

    Have you reviewed Appendix A.6 & A.8 from the below doc. to configure for block synchronized transfers?

    http://www.ti.com/lit/ug/spru234c/spru234c.pdf

    I have few suggestions below:

    Please, ensure first whether TCINTEN bit is enabled in channel OPT and only then, the interrupt pending register (IPR / IPRH) relevant bit position appropriate to the DMA event would be set on transfer completion.

    Also, ensure the TCCMODE bit in OPT which would indicate normal or early completion of data transfer and again, I would suggest you to validate the received TCC code in OPT first on the triggered DMA channel and accordingly, the corresponding bit position in IPR/IPRH would be set which is directly the TCC value and thereafter, the corresponding IER[TCC] / IERH [TCC] bit would be set to generate a EDMA completion interrupt to the DSP. By the way, the same 6-bit TCC would be posted by the TC to the CC after it receives the transfer completion signal from the destination peripheral in normal completion mode. Have you checked this?  

    Thanks & regards,  

    Sivaraj K

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