Delay between 2 bursts on UPP with a C6748 ?

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Thanks & regards,

Sivaraj K

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HI,

Thank you for your answer, I'm waiting for your help now.

I noticed also that :

if delay between 2 bursts = 20 ns => no data no EOW for the 2 nd burst with the 2nd DMA queued

if delay < 2,5 us => data are present but no EOW for this the 2nd DMA queued

if delay > 2,5 us => all is OK , Data and EOW present for the 2nd DMA queued

If you have any suggestions ? thank you in advance.

regards,

Pat

Hi Pat,

What is the state of the wait signal? Does the wait signal remain in the inactive state during the above transfers in all cases?

Regards,

Bill

Hello Bill,

Thank you very much for your answer.

yes, the WAIT signal remain in the inactive state during the above transfers in all cases .

I thought that the WAIT signal had no effect in receive mode ?

see Jo answer at e2e.ti.com/.../120588

Another suggestion ? thank you in advance for your help.

Regards.

Pat.

Hi Pat,
I'm trying to verify with the SOC designer that the wait is not used by the receive path for this part. Can you give me some details on how you are configuring the DMA accesses? What is the frequency of the internal SYSCLK1? How are you checking the PEND bit before programming the DMA descriptor fields for the second DMA?
Regards,
Bill

Hi Bill,

Thank you again for your answer.

The frequency of the internal SYSCLK1 is 360 Mhz.

This is an extract of the code for my DMA programming :
/////////////////////////////////////////////:
uPP_UPIQDS1_t uprxd1 = {0};

uprxd1.field.BCNT = 72;
uprxd1.field.LNCNT = 1;

if( (UPPR->UPRXS2 & UPP_UPIQS2_PEND_MASK) != 0)
{
// A transfer is already pending
err = DUPP_ERR_UPP_NAVAILABLE;
}
else
{
// Program the transfer
UPPR->UPRXD0 = addr;
UPPR->UPRXD1 = uprxd1.value;
UPPR->UPRXD2 = 0;
}
///////////////////////////////////////////////////////////

As you can see , I have a checking code for the pending DMA, I never failed in the error case (no error for the 1st DMA and no error for the 2nd DMA queued).
In the 3 cases of delay( t < 20 ns, t < 2,5 µs and t > 2,5 us), I'm using the same code and in the 3rd case (t > 2,5 us) all is working (I m' receiving the 2 bursts ) so I think that that the 2nd DMA is always well programmed.
The behaviour of the UPP SOC isn't the same.

Regards.

Pat.

Hi bill,

I have answered to your questions, did you have some news about the SOC designer ? thanks.

regards.