C6713 EMIF

GSR,

As I read SPRA568a, Figure 7 has an error for the x16 number, which should be 2**(N+1) to state the number of 16-bit half-words addressed by A[N:0]. This diagram shows N+1 address lines being used in A[N:0], so that will address 2**(N+1) addressable units, which for a x16 device means 16-bit wide half-words.

I have no idea what the 2**(N+2) x8 item means in Figure 7. It is the number of bytes in the addressable 2**(N+1) half-words, but that seems like a minor point to be making.

In Table 7, the author tried hard to show how to connect the EA lines to a device based on the size of that device. He tried hard to augment any descriptions elsewhere in text so that instead of an equation to explain the shifting or wrapping for different devices and different memory configuration. Honestly, I do not want to try to match your text description with the connections in Table 7. I prefer to stay with the table and just agree with it that for the C6713, EA3 will be used as the lowest byte address A0 for a x8 memory device or EA3 will be used as the lowest half-word address A1 for a x16 memory device. I hope this is meaningful enough; if not, the others may try to give you more clarifications if you need them.

Reading a single byte will be handled by the EMIF and the internal bus architecture of the device. For a x16 device without BE byte-enable lines, a minimum 16-bit read will occur but the EMIF and DSP will give you the byte you are addressing at the DSP instruction level.

Programming one byte of a x16 device will depend on that device. If it uses BEx byte enable lines, then this can be done physically as far as the EMIF is concerned, but it depends on whether the Flash device will support it.

Section 2.6 of SPRU266e is not for the C6713, but is for the C620x and C670x device EMIF peripherals. The description of shifting the address to the left is one of those things I consider confusing, especially since it does not explain which address is being shifted. But in this case, the EA lines start out representing the corresponding internal address lines, which always access 32-bit words internally inside the DSP. There is no shifting for a 32-bit wide EMIF configuration, so the EA and logical addresses match up. For a x16 EMIF configuration, the internal address is left shifted by 1 and another lower address bit is brought in to be the least-significant logic address bit; the internal address bit 2 is left shifted on the EA bus so it drives the EA3 line, still representing a 32-bit word address. And so on for the x8 implementation.

I do not know if my text descriptions help to clarify this. The best is the app note that tries to show the actual way to connect things instead of trying to explain the logic or math or science of it.

Regards,
RandyP