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GPIO4 and GPIO5 register write fails in uboot evm.c and kernel device.c file

manju gunnaiah
Expert 1715 points
Other Parts Discussed in Thread: SYSCONFIG

Hi,

GPIO4 and GPIO5 register write failing:

I have enabled clocks for all GPIO with below code in u-boot evm.c file:

__raw_writel(0x102, CM_ALWON_GPIO_0_CLKCTRL);
    while(__raw_readl(CM_ALWON_GPIO_0_CLKCTRL) != 0x102);


    __raw_writel(0x102, CM_ALWON_GPIO_1_CLKCTRL);
    while(__raw_readl(CM_ALWON_GPIO_1_CLKCTRL) != 0x102);

#define GPIO4_BASE  0x48420000

#define OMAP4_GPIO_IRQENABLE_SET_0    0x0034

__raw_writel(0x03C00000, GPIO4_BASE+OMAP4_GPIO_IRQENABLE_SET_0);


I'm able to write and read GPIO0,GPIO1,GPIO2 and GPIO3.But write to GPIO4 and GPIO5 failing.

---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

In kernel devices.c file ,also same issue.I'm able to write to GPIO0,GPIO1,GPIO2 and GPIO3.But write to GPIO4 and GPIO5 failing.:

#define GPIO_IRQENABLE_SET_0(x)    TI81XX_L4_SLOW_IO_ADDRESS(x + 0x034)

#define TI811X_GPIO4_BASE    0x48420000

__raw_writel(0x03C00000, GPIO_IRQENABLE_SET_0(TI811X_GPIO4_BASE)

  • 0
    TI__Guru** 116100 points
    Dear Manju,

    I'm able to write and read GPIO0,GPIO1,GPIO2 and GPIO3.But write to GPIO4 and GPIO5 failing.

    Fail means, what you are getting (Error code pls) ?

    Which exact device are you using ?

    TI81XX
  • 0
    TI__Guru** 116100 points
    Dear Manju,
    Can you please refer to the below TI wiki page.
    processors.wiki.ti.com/.../TI811X_PSP_04.07.00.01_Release_Notes

    It seems to be known issue.


    GPIO

    GPIO ports from banks 4 and 5 do not have any pin control registers associated with them and hence were not added to pinmux table.
    GPIO banks 4 and 5 do not have direct interrupts, but can be configured to generate intterrupt by writing following value to A8_INT_MUX_31_28 register 0x48141614

    The register values to be written are as shown below below

    For INTH_INT_ID_GPIOINT4A 28 - 1C, INTH_INT_ID_GPIOINT4B 29 - 1D , INTH_INT_ID_GPIOINT5A 30 - 1E and INTH_INT_ID_GPIOINT5B 31 - 1F

    So for GPIO 5 it should be 0x1F1E0000.

    for GPIO 4, 0x00001D1C
  • 0 in reply to Titusrathinaraj Stalin
    Expert 1715 points
    Hi Titus,

    I'm using DRA633X j5-eco.
    U-boot is not booting at all.It will not display any messages on terminal just hanged.

    When i disable write to GPIO4 and then boot the board it is booting.I'm able to see terminal messages.
  • 0 in reply to Titusrathinaraj Stalin
    Expert 1715 points
    Dear Titus,

    But i can see the below registers defined for GPIO4 and GPIO5, with their base addresses GPIO4(0x48420000) and GPIO5(0x48422000).
    I'm using currently :
    1.)34h GPIO_IRQENABLE_SET_0 Enable Set Register for Interrupt 0.
    2.)134h GPIO_OE Output Enable Register.
    3.)13Ch GPIO_DATAOUT Data Output Register.

    I need to write initial values for all above registers for GPIO4 and GPIO5.

    Can you please help me in this regard.
  • 0 in reply to manju gunnaiah
    TI__Guru**** 170625 points

    Hi Manju,

    I just test this on the J5Eco TI EVM, and I can access/read GPIO4 successful on base address 0x48420000. I am working from the u-boot prompt:

    Net:   Ethernet clocking: 0x0

    <ethaddr> not set. Reading from E-fuse

    Detected MACID:d0:ff:50:23:de:d6

    cpsw

    Hit any key to stop autoboot:  0

    TI811X_EVM#md 0x48181560 1

    48181560: 00030100    ....

    TI811X_EVM#mw 0x48181560 0x2

    TI811X_EVM#md 0x48181560 1

    48181560: 00000002    ....

    TI811X_EVM#md 0x48420000 1

    48420000: 50600801    ..`P

    TI811X_EVM#md 0x48420010 1

    48420010: 00000000    ....

    TI811X_EVM#md 0x48420034 1

    48420034: 00000000    ....

    TI811X_EVM#md 0x48420134 1

    48420134: ffffffff    ....

    As you can see from the log, first I write 0x2 in CM_ALWON_GPIO_1_CLKCTRL/0x48181560, then read successful GPIO4.GPIO_REVISION/0x48420000, GPIO4.GPIO_SYSCONFIG/0x48420010, GPIO4.GPIO_IRQENABLE_SET_0/0x48420034 and GPIO4.GPIO_OE/0x48420134.

    Can you try this at your side?

    BR
    Pavel

  • 0 in reply to Pavel Botev
    Expert 1715 points
    Dear Pavel,

    In evm.c ,i'm calling a GPIO clock write function which will write 0x102 to CM_ALWON_GPIO_1_CLKCTRL/0x48181560.

    But i was calling the GPIO4 and GPIO5 write function inside board_init function. Now i'm calling the GPIO clock write function just before the GPIO4 and GPIO5 register write function and it is successful.
    __raw_writel(0xCBFFFFFF, 0x48420134);
    __raw_writel(0xFFFF67FF, 0x48422134);

    Why is this behaviour ? Eventhough GPIO clock write function is executed before board_init function, so GPIO4 and GPIO5 write should be successful ?
  • 0 in reply to manju gunnaiah
    TI__Guru**** 170625 points

    Manju,

    Can you attach here your u-boot/board/ti/ti811x/evm.c file, the version where you get the issue?

    Note also that CM_ALWON_x registers should be programmed in the evm.c per_clocks_enable() function.

    Note also that there might be overwriting of your CM_ALWON_GPIO registers settings (if not done at the correct place) in the below file:
    u-boot/arch/arm/cpu/arm_cortexa8/ti81xx/lowlevel_init.S

    BR
    Pavel