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UART4 Multiplexing

Philip Ball
Prodigy 60 points

Hi,

As has probably been stated before, the Starterware script UARTPinMuxSetup(x) doesn't support pins other than UART0 and UART1. After looking through the AM335X documentation, we can see that whilst there is an offset for conf_uart0_rxd, conf_uart1_rxd, etc etc. there doesn't appear to be one for UART4 (or for 2,3 and 5) which is why the script doesn't work past UART1. However I read in another post that conf_mii1_rxd3/txd3 can be used to enable UART3. However, if this is true, there is no conf_mii1_rxd4/txd4 for UART4 for example. Thus looking at the offsets in the Control Module it isn't immediately obvious how to enable UART4, and I can't find anything in Starterware which gives pointers as to how to do this. Therefore, what is the method for setting up the multiplexing for UART4?

Thanks

Phil

  • 0
    TI__Intellectual 1845 points


    Hi Philip,

    UART4 is multiplixed through the MII1_TXD3 and MII1_TXD2 pins in the GP EVM AM335x board.

    For UART4 you have to do pinmux settings on CONTROL_CONF_MII1_TXD3 for RXD and CONTROL_CONF_MII1_TXD2 for TXD pin of UART4.

    The following snippet of code should work for EVM board for UART4 TXD and RXD pins.

    You can refer the schematics of the board you are using and the Control Module chapter of the TRM.

    /* RXD */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD3) =
    (CONTROL_CONF_MII1_TXD3_CONF_MII1_TXD3_PUTYPESEL |
     CONTROL_CONF_MII1_TXD3_CONF_MII1_TXD3_RXACTIVE |
      CONTROL_CONF_MUXMODE(3)));

    /* TXD */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD2) =
     (CONTROL_CONF_MII1_TXD2_CONF_MII1_TXD2_PUTYPESEL |
       CONTROL_CONF_MUXMODE(3));
      
    Regards
    Anant Pai

  • 0 in reply to Anant Pai
    Prodigy 60 points

    Hi Anant,

    Many thanks for the reply; I tried out the snippet you provided, but it doesn't seem to be working for me. I'm using a Beaglebone, and looking at the schematics, UART4_RXD seems to be linked to MII1_RX_DV and UART4_TXD appears to be linked to MDIO_CLK. However, even with these offsets I don't get anything out. The code written does work as enabling UART1 results in correct operation. In addition, I'm not entirely sure how the MUXMODE(n) setting works. It's stated that n=7 results in reset, but other modes are not explained.

    Regards,
    Phil

  • 0 in reply to Philip Ball
    Prodigy 60 points

    Having had a look at the Pin Mux Utility, the pin muxes on MII1_TXD3/2 are UART4_R/TXD_MUX0; does the MUX(n) suffix matter in this case? I've tried enabling MUX0 through to 2 individually with no success.

    Regards
    Phil

  • 0 in reply to Philip Ball
    Prodigy 60 points

    Turns out my UART4 clock setup was causing the lack of signals; for some reason what I'd written would work for UART1, but not UART4. For reference, I'll include my updated and working UART4 clock setup:

        /* Alternative UART4 clock setup */
        HWREG(SOC_CM_PER_REGS + CM_PER_UART4_CLKCTRL) |=
              CM_PER_UART4_CLKCTRL_MODULEMODE_ENABLE;

        /* Waiting for MODULEMODE field to reflect the written value. */
        while(CM_PER_UART4_CLKCTRL_MODULEMODE_ENABLE !=
              (HWREG(SOC_CM_PER_REGS + CM_PER_UART4_CLKCTRL) &
               CM_PER_UART4_CLKCTRL_MODULEMODE));