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Memory access ordering

Patrick Ruf
Genius 4810 points

Hi,

We are using StarterWare on a AM335x processor. In relation to the SYS/BIOS Ind. SDK code I have the following question regarding memory access ordering on Cortex-A8 processor:

MMU is enabled and all the peripheral register after address 0x44000000 are in a memory range that is defined as "Device, shareable, execute never"

As an example I want to access a PHY over the MDIO module within the PRUICSS. Therefore I do the following:

- Write the needed information with the GO flag set to the PRUICSS MDIO MII USRACCESS0 register
- Wait until the GO flag in the USRACCESS0 register is cleared by the peripheral

The code looks like that:

    // Lesezugriff auf MDIO auslösen
    HWREG(SOC_PRUICSS_REGS+PRUICSS_MII_MDIO_USRACCESS0)=(PRUICSS_MII_MDIO_USRACCESS0_GO |
                                                         (phyaddr<<PRUICSS_MII_MDIO_USRACCESS0_PHYADR_SHIFT) |
                                                         (regoffset<<PRUICSS_MII_MDIO_USRACCESS0_REGADR_SHIFT));
    // Warten, bis der Lesezugriff ausgeführt wurde
    while(HWREG(SOC_PRUICSS_REGS+PRUICSS_MII_MDIO_USRACCESS0) & PRUICSS_MII_MDIO_USRACCESS0_GO);

Do I need a "DMB" instruction in between the write operation and the while() loop?
The question is, is it possible that the processor is already reading the register although the write to the same register ist not finished yet or is this blocked by the memory type "Device"?

Thanks and best regards,
Patrick

  • 0
    Genius 4810 points

    Hi,

    Does anyone from the TI ARM experts have an idea on this topic?

    Thanks and best regards,
    Patrick

  • 0 in reply to Patrick Ruf
    TI__Mastermind 43610 points

    Hi,

    I found following public links quite useful.To answer specific question, I do not think DMB is required if you are polling for side effect of the action (setting GO bit) in the peripheral control register. Actually DMB won't work at all if you are using barrier for this scenario you need DSB SYS...

    http://events.linuxfoundation.org/sites/events/files/slides/weak-to-weedy.pdf 

    http://community.arm.com/groups/processors/blog/2011/10/19/memory-access-ordering-part-3--memory-access-ordering-in-the-arm-architecture

    also see below some points from an internal source 

    >Most accesses to DEVICE memory is ordered by DEVICE space rules [buffered(pipe lining of stores), delivered in order to a device page and accesses not combined - read values not forwarded from writes ]

    > If DEVICE is larger than page size, use DMB NSH to order accesses from the processor only

    >L3 masters ( Eg:- PRU-ICSS, EDMA) usually don't need barriers to function correctly - they are not as weakly ordered

    >Two device interactions where memory barriers are useful - CPU write memory for an access by L3 master (PRU-ICSS) or completion barrier for I/O access

      In both scenarios you need DSB SYS as barrier. For completion status of peripheral control register write, one can poll corresponding status register of the peripheral instead of using barrier instruction.