Hi,
When enabling of AM3352 caches I'm seeing random data and prefetch abort exceptions.
MMU seems to be correctly set up.
Data and Instruction caches are then enabled.
I disassembled the code and the instructions generating the code are legit SDRAM addresses.
When the caches are disabled, everything works fine.
The app is in C and uses Ti Starterware and ThreadX.
Can you suggest some ideas of what to check? Tests to narrow down the problem?
Could this be related to SDRAM controller timing setup?
Thanks a lot,