Other Parts Discussed in Thread: SYSCONFIG, , SYSBIOS
Tool/software: Starterware
HI,
I'm using a beaglebone black, CCS 6.1 with Starterware 2.0.1.1 for my project. The interfaced in configured in non_mux mode with address 0x0100 0000, 16Mb with GPMC_csn0.
The following code is used to Configure the GPMC :
#define CS_WR_OFF_TIME 0x1E
#define CS_RD_OFF_TIME 0x1E
#define CS_ON_TIME 0x01
#define ADV_ON_TIME 0x02
#define ADV_RD_OFF_TIME 0x04
#define ADV_WR_OFF_TIME 0x04
#define OE_ON_TIME 0x0A
#define OE_OFF_TIME 0x19
#define WE_ON_TIME 0x0A
#define WE_OFF_TIME 0x19
#define RD_CYCLE_TIME 0x1F
#define WR_CYCLE_TIME 0x1F
#define RD_ACCESS_TIME 0x19
#define WR_DATA_ON_ADMUX 0x06
#define WR_ACCESS_TIME 0x00
#define CYC2CYC_DELAY 0x05
#define CS0_BASE_ADDR 0x01 // base_addr (0x01-0x1F)
#define CS0_MASK_ADDR GPMC_CS_SIZE_16MB // max cs size = 16 mb
#define LCD_WRITE(x) (*(volatile unsigned int *)(x))
#define LCD_BASE 0x01000000
#define LCD_OFFSET (LCD_BASE + 0x01)
void GPMC_Init(void)
{
unsigned int csNum = 0;
unsigned int baseAddr = SOC_GPMC_0_REGS;
unsigned int conf = 0;
//enable clock to GPMC module
HWREG(SOC_CM_PER_REGS + CM_PER_GPMC_CLKCTRL) = (CM_PER_GPMC_CLKCTRL_MODULEMODE_ENABLE << CM_PER_GPMC_CLKCTRL_MODULEMODE_SHIFT);
//check to see if enabled
while((HWREG(SOC_CM_PER_REGS + CM_PER_GPMC_CLKCTRL) & (CM_PER_GPMC_CLKCTRL_IDLEST)));
GPMCIdleModeSelect(baseAddr, GPMC_IDLEMODE_FORCEIDLE);
//reset the GPMC module
GPMCModuleSoftReset(baseAddr);
while (GPMCModuleResetStatusGet(baseAddr) == GPMC_SYSSTATUS_RESETDONE_RSTONGOING);
GPMCIdleModeSelect(baseAddr,GPMC_SYSCONFIG_IDLEMODE_NOIDLE);
HWREG(baseAddr + GPMC_IRQENABLE) = 0x0;
//--------------------------------------- CS0 SRAM Config ---------------------------------------
//GPMCTimeOutStartValSet(GPMC_BASE,0);
HWREG(baseAddr + GPMC_TIMEOUT_CONTROL) = 0x0;
GPMCDevTypeSelect(baseAddr, csNum, GPMC_DEVICETYPE_NORLIKE);
GPMCDevSizeSelect(baseAddr, csNum, GPMC_DEVICESIZE_16BITS);
GPMCDevPageLenSet(baseAddr, csNum, GPMC_DEV_PAGELENGTH_FOUR);
GPMCAddrDataMuxProtocolSelect(baseAddr, csNum, GPMC_MUXADDDATA_NOMUX);
GPMCTimeParaGranularitySelect(baseAddr, csNum, GPMC_TIMEPARAGRANULARITY_X2);
conf = GPMC_CS_TIMING_CONFIG(CS_WR_OFF_TIME, CS_RD_OFF_TIME, GPMC_CS_EXTRA_NODELAY, CS_ON_TIME);
GPMCCSTimingConfig(baseAddr, csNum, conf);
//conf = GPMC_ADV_TIMING_CONFIG(0, 0, ADV_WR_OFF_TIME, ADV_RD_OFF_TIME, GPMC_ADV_EXTRA_NODELAY, 0, ADV_ON_TIME);
//GPMCADVTimingConfig(baseAddr, csNum, conf);
conf = GPMC_WE_OE_TIMING_CONFIG(WE_OFF_TIME, GPMC_WE_EXTRA_NODELAY, WE_ON_TIME, 0, OE_OFF_TIME, GPMC_OE_EXTRA_NODELAY, 0, OE_ON_TIME);
GPMCWEAndOETimingConfig(baseAddr, csNum, conf);
conf = GPMC_RDACCESS_CYCLETIME_TIMING_CONFIG(RD_CYCLE_TIME, WR_CYCLE_TIME, RD_ACCESS_TIME, 0);
GPMCRdAccessAndCycleTimeTimingConfig(baseAddr, csNum, conf);
//GPMCWrAccessAndWrDataOnADMUXBusTimingConfig(baseAddr, csNum, WR_ACCESS_TIME, WR_DATA_ON_ADMUX);
conf = GPMC_CYCLE2CYCLE_BUSTURNAROUND_TIMING_CONFIG(CYC2CYC_DELAY, GPMC_CYCLE2CYCLESAMECSEN_C2CDELAY, GPMC_CYCLE2CYCLEDIFFCSEN_NOC2CDELAY, 0 );
GPMCycle2CycleAndTurnArndTimeTimingConfig(baseAddr, csNum, conf);
GPMCBaseAddrSet(baseAddr, csNum, CS0_BASE_ADDR);
GPMCMaskAddrSet(baseAddr, csNum, CS0_MASK_ADDR);
GPMCCSConfig(baseAddr, csNum, GPMC_CS_ENABLE);
}
void GPMC_PinConfig(void)
{
//MODE SWITCH
CPUSwitchToPrivilegedMode();
//CPUSwitchToUserMode();
//PIN MUX
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(8)) = CONTROL_CONF_MUXMODE(0); /* Mapping GPMC_AD8 => GPMC_AD8 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(9)) = CONTROL_CONF_MUXMODE(0); /* Mapping GPMC_AD9 => GPMC_AD9 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(10)) = CONTROL_CONF_MUXMODE(0); /* Mapping GPMC_AD10 => GPMC_AD10 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(11)) = CONTROL_CONF_MUXMODE(0); /* Mapping GPMC_AD11 => GPMC_AD11 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(12)) = CONTROL_CONF_MUXMODE(0); /* Mapping GPMC_AD12 => GPMC_AD12 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(13)) = CONTROL_CONF_MUXMODE(0); /* Mapping GPMC_AD13 => GPMC_AD13 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(14)) = CONTROL_CONF_MUXMODE(0); /* Mapping GPMC_AD14 => GPMC_AD14 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(15)) = CONTROL_CONF_MUXMODE(0); /* Mapping GPMC_AD15 => GPMC_AD15 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_WEN) = CONTROL_CONF_MUXMODE(0); /* Mapping GPMC_WEN => GPMC_WEN */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_OEN_REN) = CONTROL_CONF_MUXMODE(0); /* Mapping GPMC_OEN_REN => GPMC_OEN_REN */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_CSN(0)) = CONTROL_CONF_MUXMODE(0); /* Mapping GPMC_CSN0 => GPMC_CSN0 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_CSN(3)) = CONTROL_CONF_MUXMODE(0); /* Mapping GPMC_CSN3 => GPMC_CSN3 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_CLK) = CONTROL_CONF_MUXMODE(0); /* Mapping GPMC_CLK => GPMC_CLK */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_WAIT0) = CONTROL_CONF_MUXMODE(0); /* Mapping GPMC_WAIT0 => GPMC_WAIT0 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(0)) = CONTROL_CONF_MUXMODE(1); /* Mapping LCD_DATA0 => GPMC_A0 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(1)) = CONTROL_CONF_MUXMODE(1); /* Mapping LCD_DATA1 => GPMC_A1 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(2)) = CONTROL_CONF_MUXMODE(1); /* Mapping LCD_DATA2 => GPMC_A2 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(3)) = CONTROL_CONF_MUXMODE(1); /* Mapping LCD_DATA3 => GPMC_A3 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(4)) = CONTROL_CONF_MUXMODE(1); /* Mapping LCD_DATA4 => GPMC_A4 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(5)) = CONTROL_CONF_MUXMODE(1); /* Mapping LCD_DATA5 => GPMC_A5 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(6)) = CONTROL_CONF_MUXMODE(1); /* Mapping LCD_DATA6 => GPMC_A6 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(7)) = CONTROL_CONF_MUXMODE(1); /* Mapping LCD_DATA7 => GPMC_A7 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_VSYNC) = CONTROL_CONF_MUXMODE(1); /* Mapping LCD_VSYNC => GPMC_A8 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_HSYNC) = CONTROL_CONF_MUXMODE(1); /* Mapping LCD_HSYNC => GPMC_A9 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_PCLK) = CONTROL_CONF_MUXMODE(1); /* Mapping LCD_PCLK => GPMC_A10 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_AC_BIAS_EN) = CONTROL_CONF_MUXMODE(1); /* Mapping LCD_AC_BIAS_EN => GPMC_A11 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(8)) = CONTROL_CONF_MUXMODE(1); /* Mapping LCD_DATA8 => GPMC_A12 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(9)) = CONTROL_CONF_MUXMODE(1); /* Mapping LCD_DATA9 => GPMC_A13 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(10)) = CONTROL_CONF_MUXMODE(1); /* Mapping LCD_DATA10 => GPMC_A14 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(11)) = CONTROL_CONF_MUXMODE(1); /* Mapping LCD_DATA11 => GPMC_A15 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(12)) = CONTROL_CONF_MUXMODE(1); /* Mapping LCD_DATA12 => GPMC_A16 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(13)) = CONTROL_CONF_MUXMODE(1); /* Mapping LCD_DATA13 => GPMC_A17 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(14)) = CONTROL_CONF_MUXMODE(1); /* Mapping LCD_DATA14 => GPMC_A18 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(15)) = CONTROL_CONF_MUXMODE(1); /* Mapping LCD_DATA15 => GPMC_A19 */
;
}
After doing this, i'm trying to write a word in the address 0x0100 0000 but the application crashes at this point with undefined handler.
LCD_WRITE(LCD_OFFSET)=0xaa00;
Here are GPMC_CONFIG7 registers:
GPMC_CONFIG1_0 0x00001010
GPMC_CONFIG2_0 0x001E1E01
GPMC_CONFIG3_0 0x22060514
GPMC_CONFIG4_0 0x190A190A
GPMC_CONFIG5_0 0x00191F1F
GPMC_CONFIG6_0 0x8F070580
GPMC_CONFIG7_0 0x00000F41
Please let me know, if this is the right way to do and also why it crashes when i'm trying to write to GPMC address. Please suggest.
Thanks
