How to accelerate the memory access speed of syslink?

Feng Xiao Ming,

To confirm software versions, are you using the following releases?

EZSDK 5.05.02
SysLink 2.20.02.20

The ex04_sharedregion example builds both debug and release binaries. I assume you are using the release binary.

The example has configured Shared Region #1 as non-cacheable memory. That means the DSP memory accesses are long distance, which is probably the reason for the significant delay. I would suggest you try to make the memory cacheable and see if that improves the performance. However, you will be responsible for managing the cache coherency.

The cacheable property of the memory is a per-processor attribute. This means you can make it cacheable from the DSP but not from the ARM. If you are only interested in the DSP side, then I suggest we start with this approach.

On the DSP, the memory cache property is controlled by the MAR bits. Each bit controls a 16 MB section of memory. The example is currently using the same 16 MB section for both Shared Region #0 and Shared Region #1. We don't want to change SR_0, so lets pick a new 16 MB section in the memory map. How about we move SR_1 to just before SR_0. Your new memory map would look like this.

/* Memory Map for ti.platforms.evmTI816X
 *
 * 8000_0000 - 8FFF_FFFF 1000_0000 ( 256 MB) External Memory
 * ------------------------------------------------------------------------
 * 8000_0000 - 84FF_FFFF  500_0000 ( 80 MB) Linux
 * 8500_0000 - 8CFF_FFFF  800_0000 ( 128 MB) --------
 * 8D00_0000 - 8DFF_FFFF  100_0000 ( 16 MB) SR_1 (program shared region)
 * 8E00_0000 - 8E00_FFFF    1_0000 ( 64 KB) SR_0 (ipc)
 * 8E01_0000 - 8EFF_FFFF   FF_0000 ( ~15 MB) --------
 * 8F00_0000 - 8FFF_FFFF  100_0000 ( 16 MB) DSP_PROG (code, data)
 */

To actually change the memory map, you need to edit the config.bld file and update the base and len properties of the SR_1 object.

ex04_sharedregion/shared/config.bld

var SR_1 = {
        name: "SR_1", space: "data", access: "RWX",
        base: 0x8D000000, len: 0x1000000,
        comment: "SR#1 Memory (16 MB)"
    };

Next, you need to mark Shared Region #1 as cacheable. This is done in the Dsp.cfg file. Change the cacheEnable property to true as follows.

ex04_sharedregion/dsp/Dsp.cfg

/* configure SharedRegion #1 (IPC) */
var SR1Mem = Program.cpu.memoryMap["SR_1"];

SharedRegion.setEntryMeta(1,
    new SharedRegion.Entry({
        name:           "SR1",
        base:           SR1Mem.base,
        len:            SR1Mem.len,
        ownerProcId:    MultiProc.getIdMeta("HOST"),
        cacheEnable:    true,
        isValid:        true
    })
);

Now, you need to modify your DSP code to write-back and invalidate the memory after it has been written. Do this right after the loop which converts the string to lowercase.

    /* 6. convert lowercase string to uppercase */
    while (*bufferPtr != 0) {
        if (*bufferPtr >= 0x61 && *bufferPtr <= 0x7A) {
            *bufferPtr = *bufferPtr - 0x20;
        }
        bufferPtr++;
    }

    /* writeback and invalidate the cache */
    Cache_wbInvAll();

You will need to include <ti/sysbios.hal.Cache.h> in your Server.c file. And you will need to add the following to your Dsp.cfg script.

xdc.useModule('ti.sysbios.hal.Cache');

Be sure to rebuild both programs (ARM and DSP).

I hope this helps.

~Ramsey