SDSPITiva_HWAttrs DETAILS

Yes, i am wondering the same thing. Looking at the fatsd_TivaTM4C1294NCPDT demo, channel 0 (boosterpack 1 headers) uses SSI2 and PD1 as MOSI but PB1 as TX while channel 1 (boosterpack 2 headers) uses SSI3 and PQ2 as both MOSI and TX. Is that correct for channel 0? What I can see PB1 isn't even on the boosterpack 1 headers.

const SDSPITiva_HWAttrs sdspiTivaHWattrs[EK_TM4C1294XL_SDSPICOUNT] = {
    {
        SSI2_BASE,          /* SPI base address */

        GPIO_PORTD_BASE,    /* The GPIO port used for the SPI pins */
        GPIO_PIN_3,         /* SCK */
        GPIO_PIN_0,         /* MISO */
        GPIO_PIN_1,         /* MOSI */

        GPIO_PORTC_BASE,    /* Chip select port */
        GPIO_PIN_7,         /* Chip select pin */

        GPIO_PORTB_BASE,    /* GPIO TX port */
        GPIO_PIN_1,         /* GPIO TX pin */
    },
    {
        SSI3_BASE,          /* SPI base address */

        GPIO_PORTQ_BASE,    /* The GPIO port used for the SPI pins */
        GPIO_PIN_0,         /* SCK */
        GPIO_PIN_3,         /* MISO */
        GPIO_PIN_2,         /* MOSI */

        GPIO_PORTP_BASE,    /* Chip select port */
        GPIO_PIN_4,         /* Chip select pin */

        GPIO_PORTQ_BASE,    /* GPIO TX port */
        GPIO_PIN_2,         /* GPIO TX pin */
    }
};

EK_TM4C1294XL_initSDSPI doesn't initialize any pins on port b either.

/Ruben
 

Hello Ruben,

    I still don't know the answer of my query, but the reason for asking this in this forum was to successfully port the SDSPI port from SSI2 to SSI0. In my custom board, the SDSPI uses SSI0 port on PA2, PA4 & PA5.

    For the said last parameter, I made the structure point to MOSI pin & it worked.

    Although, its better to understand first & then implement, but it somehow worked fine. I even checked up with the doxygen documentation, but cudn't figure out about the last element of the structure. I wud suggest that you make the last element point to MOSI pin of SDSPI set.

Thanks

Regards

Soumyajit

Yes, I will try that - Thanks.

I am actually using our own board using SSI3 but looking at the examples for the TM4C1294 Connected LaunchPad.

After some further investigations I have found this: At some part of the initialization of the SD card, the TX (MOSI) needs to be kept at high level while several clocks are sent to it in order to get it into SPI mode. SDSPITiva.c shows that the TX pin is set to an output at high level while 10 bytes are clocked out. After that, the pin is set back to SPI MOSI. In this case, the MOSI pin in the hwAttrs could be used but I guess for some other processors you might need a separate GPIO pin for this operation. But I also guess that if you can't mix SPI and GPIO modes for individual pins for the SSI you coud just set the entire SSI channel to GPIO and manually clock out the clock signals so I am not sure of the reason...

/*
 *  ======== send_initial_clock_train ========
 *  Function to get the SDCard into SPI mode
 *
 *  @param  hwAttrs     Pointer to hardware attributes
 */
static Void send_initial_clock_train(SDSPITiva_HWAttrs const *hwAttrs)
{
    UInt            i;
    SDSPIDataType   dat;

    /* Deselect the SD card. */
    GPIOPinWrite(hwAttrs->portCS, hwAttrs->pinCS, hwAttrs->pinCS);

    /* Switch the SPI TX line to a GPIO and drive it high too. */
    GPIOPinTypeGPIOOutput(hwAttrs->portTX, hwAttrs->pinTX);
    GPIOPinWrite(hwAttrs->portTX, hwAttrs->pinTX, hwAttrs->pinTX);

    /*
     * Send 10 bytes over the SPI bus. This causes the clock to toggle several
     * times to get the SD Card into SPI mode.
     */
    for (i = 0; i < 10; i++) {
        /*
         * Write DUMMY data. SSIDataPut() waits until there is room in the
         * FIFO.
         */
        SSIDataPut(hwAttrs->baseAddr, 0xFF);

        /* Flush data read during data write. */
        SSIDataGet(hwAttrs->baseAddr, &dat);
        //rxSPI(hwAttrs);
    }

    /* Revert to hardware control of the SPI TX line. */
    GPIODirModeSet(hwAttrs->portSPI, hwAttrs->pinMOSI, GPIO_DIR_MODE_HW);

    Log_print1(Diags_USER1, "SDSPI:(%p) initialized SD card to SPI mode",
                             hwAttrs->baseAddr);
}

/Ruben

Hmm, got it... Thanks

Soumyajit,

this hwattrs of the SDSPI driver has been simplified in the meantime with TI-RTOS 2.10.01.38.

This redundancy was simplified to the snippet shown below:

typedef struct SDSPITiva_HWAttrs {
    /*!< SSI Peripheral's base address */
    SDSPIBaseAddrType baseAddr;

    /*!< SSI port SCK */
    uint32_t portSCK;
    /*!< SSI SCK pin */
    uint32_t pinSCK;

    /*!< SSI port MISO */
    uint32_t portMISO;
    /*!< SSI MISO pin */
    uint32_t pinMISO;

    /*!< SSI port MOSI */
    uint32_t portMOSI;
    /*!< SSI MOSI pin */
    uint32_t pinMOSI;

    /*!< GPIO Port used for the chip select */
    uint32_t portCS;
    /*!< GPIO Pin used for the chip select */
    uint32_t pinCS;
} SDSPITiva_HWAttrs;