Hello,
I am implementing a hard real time algorithm on a c5517 chip, using DSP/BIOS. My application features an intense and tightly synchronized activity of the on-board DMA units. I noticed that the system clock interrupt (which I have set on timer-1) can stall the Switched Central Resource (SCR) for a few clock cycles.
This is critical because, when a DMA transfer is issued by an event on timer-0, it is sometimes delayed by a few clock cycles, if the two events (the SYSTEM-CLOCK event on timer-1 and the DMA synchronization event) happen one close to each other. This cannot be tolerated in my application, I need the SCR clean and free when a DMA transfer is issued. Note that every task and transfer is meant to be synchronized, so I will take care of letting the SCR free for the DMA with the proper margins.
If the two timers run asynchronously the occasional overlaping of the two aforementioned events cannot be avoided. The Idea I'm working on at the moment is to synchronize the timers generating the two events and introduce a deterministic and constant phase shift between the two, so that I can be sure that the CLK_isr has returned, and freed the SCR, before the DMA transfers are triggered by timer-0.
To have a better understanding of how and why the SYSTEM-CLOCK interrupt needs to transfer data over the SCR (maybe acknowledgement with the timer, reading or writing its registers, I don't know yet) I would need to read the code that is being run when CLK_isr is called.
Where can I find it?
Thanks for your help.
