Hi,
I am designing with SN75DP139. Could you pls provide me the schematic and PCB layout reference design of this part?
Thanks,
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Attached are two different reference schematics for the DP139 in a GPU source application supporting with an HDMI interface or DVI. For layout, I would suggest looking over the HS layout guidelines. What is your application? The 139 should be placed close to the final TMDS interface for best signal integrity at the customer interface (DVI or HDMI). SMT connectors are always encouraged for minimal signal discontinuities.
0830.Texas_Instruments_DisplayPort_Design_Guide_Rev1.1.pdf
1373.SN75DP139_REFERENCE_SCHEMATIC_HDMI_Rev_C.pdf7536.SN75DP139_REFERENCE_SCHEMATIC_DVI_Rev_C.pdf
Hi Ken,
I use SN75DP139 in my design, but during layout, I found that the chip can't be directly connect to HDMI connector. The P trace and N trace have to be swaped.
Do you know the reason? Do you have a reference layout you can share with me?
Thanks,
Tony
The reference board we have swaps the input pins and the output pins with no vias. Just to be clear, the input DP main link input 3n is connected to pin 48 of the RGZ package which is label as the "IN_D4+" signal. DP main link input 3p would be connected to pin 47 which is the "IN_D4-". As you can see the input signals are swapped. The output is also swapped. "OUT_D4+", pin 13, would be connected to pin 12 of the HDMI connector for signal TXCn and "OUT_D4-", pin 14, would be connected to pin 10 of the HDMI connector for signal TXCp.
DP input: from sink connector J1
ML_IN0_N = J1,10 to cap to U1,39 |
ML_IN0_P = J1,12 to cap to U1,38 |
ML_IN1_N = J1,7 to cap to U1,42 |
ML_IN1_P = J1,9 to cap to U1,41 |
ML_IN2_N = J1,4 to cap to U1,45 |
ML_IN2_P = J1,6 to cap to U1,44 |
ML_IN3_N = J1,1 to cap to U1,48 |
ML_IN3_P = J1,3 to cap to U1,47 |
TMDS Output to HDMI Connector J2
TMDS_SINK_CLK_N = J2,10 to U1,14 |
TMDS_SINK_CLK_P = J2,12 to U1,13 |
TMDS_SINK_D0_N = J2,7 to U1,17 |
TMDS_SINK_D0_P = J2,9 to U1,16 |
TMDS_SINK_D1_N = J2,4 to U1,20 |
TMDS_SINK_D1_P = J2,6 to U1,19 |
TMDS_SINK_D2_N = J2,1 to U1,23 |
TMDS_SINK_D2_P = J2,3 to U1,22 |
HI Ken,
Can I get ibis or hspice model files for this sn75dp139 chip?
Regarding the Receiver equailization, may I know how much in db? If I have a cable between DISPLAYPORT source and SN75DP139 input how much cable length Receiver Equilizer can recover?
Thanks in advance,
PD
Hi Ken,
Could I have the PCB layout files and BOM for the SN75DP139 DP/HDMI/DVI Ref Design? I have a customer who would like to refer to this.
Thank You very much
Best Regards,
Chee Boon
Hi Chee-Boon
In the next link you can find layout files & schematics.
https://sps04.itg.ti.com/sites/ibu/cci/CCI%20Product%20Information/Forms/AllItems.aspx?RootFolder=%2Fsites%2Fibu%2Fcci%2FCCI%20Product%20Information%2FDP%20Devices%2FDP139&View=%7bFEBB1BE2-AA77-4741-A70D-1923ECD98CC5%7d
Regards.
JC
Hi Jose,
Can you verify that the link you posted is correct? It appears to be broken.
If possible, I would like to have the BOM as well.
Thank You
Best Regards,
Chee Boon
Hi Chee-Boon.
The link is OK, maybe you're not authorized to access that link.
Since this is sensitive information, we can not share on open forum, so please, send me an e-mail with all the information about business case so I can share with you that information needed. (Also BOM).
Best regards.
JC
JoseCarlos.Gil@ti.com