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Questions regarding TUSB320LAI/TUSB320HAI

user4501538
Prodigy 200 points

Hi Sir,

I have some questions regarding TUSB320LAI/TUSB320HAI when I do the evaluation. Can you please kindly help to answer these questions? Thanks a lot in advance.

Questions regarding TUSB320LAI/TUSB320HAI:

  1.  In the datasheet page 3,  it is stated in Pin Function stable that both EN_N (TUSB320L) and EN(TUSB320H) must be held low at least for 50 ms after VDD has reached its valid voltage level. Should it be “EN must be held LOW at least for 50 ms after VDD has reached its valid voltage level. EN_N must be held HIGH at least for 50 ms after VDD has reached its valid voltage level.”?
  2.  In datasheet page 17, what is the value will be in the Register 0x08[5:4] if the device is configured at UFP mode and operates at unattached state? In table 3 (page 12), there is an option for OUT1/OUT2 outputs "Default Current in Unattached State". I cannot find the similar option in Register 0x08[5:4].
  3.  In datasheet page 17, what is the relationship between Register 0x08[3:1]= 100 (audio accessory) and Register 0x08[3:1]= 101(audio charged thru accessory)? My understanding is 100 = passive audio accessory. And audio accessory = passive audio accessory + audio charged thru accessory, is that right? However, according my test, when 0x08[5:4]= 10, 0x08[3:1] is 100, not 101?
  4.  In the datasheet page 19 & 20, what is the difference between 0x0A[0] & 0x45[2]? My understanding is, if this bit is set, the CC1 & CC2 are configured to high impedance state (disable Rp & Rd). can you please confirm?
  5.  In the datasheet page 19, what are the applications for DISABLE_UFP_ACCESSORY bit?
  6.  In the datasheet page 18, a read and write 1 to 0x09[4] bit to clear the interrupt bit, or simply a write 1 to 0x09[4] to clear the interrupt bit?