XIO2001: Link training detect state delay

Massimo Martelli

Part Number: XIO2001

Hello,

according to the PCIe 2.0 specs, I understand that "a component must enter the LTTS detect state within 20ms of the end of Fundamental Reset".

In the XIO2001 Datashet page 27 we read that "The bridge starts link training within 80 ms after GRST is deasserted". Is it an exception to the specifications?

Can you please comment?

Thanks, best regards

Massimo

over 7 years ago

0 Elias Villegas M. over 7 years ago

TI__Guru* 76130 points

Hello,
Your observation is correct. The 80ms is specified by design. I don't have the exact time and it may vary from power cycles, however any system will wait for a minimum of 100ms prior to start link training, we've never seen issues with this kind of processes.
Regards

0 Massimo Martelli over 7 years ago in reply to Elias Villegas M.

Prodigy 90 points

Hi Elias,

in the original question I should have referred to PERSTn (the PCIe Fundamental Reset).

The datasheet states that "The XIO2001 starts link training within 80 ms after PERST is deasserted", and this looks like an exception to the specification that requires “20ms max”.
Or is it a typo error in the documentation? Can you please clarify?

best regards
Massimo

0 Elias Villegas M. over 7 years ago in reply to Massimo Martelli

TI__Guru* 76130 points

I see.
It might be a typo indeed, I will investigate this and get back to you.
Regards

0 Massimo Martelli over 7 years ago in reply to Elias Villegas M.

Prodigy 90 points

Hi Elias,

any news on this? Did you get more details?

thanks, best regards

Massimo

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XIO2001: Link training detect state delay