XIO2001: REFCLK input voltage level definition for XIO2001

Hi Niels,

Your REFCLK looks okay, but there may be an issue with the PLL not locking correctly during the power-up sequence. GRST needs to be asserted after VDD_15/VDDA_15, VDD_33/VDDA_33 and PCIR. See below waveform for reference (from page 22 of the datasheet):

Can you try asserting GRST after power-up to see if you get an output clock? Additionally, a 0.2uF cap needs to be placed on GRST to ensure it is asserted after the aforementioned parameters.

Regards,

I.K. 

Hello I.K.

The 1.5V are made by an LDO from the 3.3V, so they ramp up quite simultaneously.

PCIR has a 1k Ohm Pullup to 3.3V and a 100nF Capacitor to GND.

GRST# is left unconnected as it has an internal Pullup. We use the XIO2001 in the BGA package. So despite the fact that GRST# is located in one corner of the grid, it will be hard to attach anything to it. But I will try.

As a test, I have modified my REFCLK-Termination from 100 Ohm differential to two 100 Ohm resistors connected to GND. The result is that the common mode voltage is reduced, differential voltage swing is reduced, but the XIO2001 is able to generate the 33MHz PCI-Clock:

Next, I removed the Termination completely. The REFCLK looks quite ugly, but the XIO2001 is able to work with it:

Do you have any explanation for this behaviour?

Regads, Niels

Dear I.K.

here are some pictures of my power-up sequence:

A closeup on the rising power-supplies:

And an image that inculdes the PERST signal:

As an additional test, I removed the capacitor from PCIR so it ramps up simultaneously with the 3.3V supply. This does not change the missbehaveourof the PCI-clock.

Good morning I.K.,

the following picture shows the PCI-Clock (CH 1), REFCLK+ (CH 3), REFCLK- (CH 4) and the differential REFCLK (CH M).

And here's another one that shows only REFCLK+ and REFCLK- as a closeup. This picture was taken with a fade-out ime of 30 seconds:

Does this help?

In principle, this is exactly the termination that is recommended for the LVDS clock driver: A 100 Ohm resistor between REFCLK+ and REFCLK-. But exactly this configuration fails.

If I change the termination to two separate 100 Ohm resistors, one connected from REFCLK+ to GND and the other from REFCLK- to GND, the XIO2001 works.

The XIO2001 also works if I remove the termination from REFCLK.

Are there any limitations for the DC common mode input voltage of REFCLK?

Regards, Niels

Hy I.K.

here is another scope shot of my clocks.

I modified the termination toachieve 850mV Common Mode Voltage, and the XIO2001 works:

(Fade-out ime for this picture was 30 seconds)

Regards, Niels

Hi I.K.,

With 100 Ohm differential termination, REFCLK has a DC common mode voltage of 1250mV, which is a bit more than the 650mV you sugeseted as maximum for the XIO2001.
You can see it in my message from "Jul 7, 2017 10:34 AM"

I already tried 100 Ohm single-ended termination on each REFCLK line and get no valid output clock (my message from "Jul 6, 2017 11:56 AM")

But why does it work without any termination?
The REFCLK DC common mode voltage without termination is the same as with 100 Ohm differential termination: 1250mV
Only the differential voltage swing differs:
400mV for 100 Ohm differential Termination
1200mV without termination

Do you have any explanation?

Regards, Niels

Hello I.K.,

here is the scope shot with 50 Ohm single ended Termination (putting a 50 ohm resistor to ground on REFCLK+ and a 50 ohm resistor to ground on REFCLK-):

The differential volatege swing is quite small ( app. 300mV), but it works.

And now the scope shot with 200 Ohm differential termination:

It works, despite the fact that it'S DC common mode voltage is 1250mV.

The clock source is a DSC1103CI5-100.000

DSC1103_DSC1123_Datasheet.pdf

This looks like a DC common mode voltage dependant differential voltageswing requirement, but I can't imagine that TI would build such a crazy input buffer.

Do you have any explanation for this behaviour?

Regards, Niels

Hi Niels,

I hope you are enjoying your weekend. Thank you for explaining the difference between 50 ohm singled-ended termination and 100 ohm differential termination. That helped lead me to the conclusion below:

Though you are feeding REFCLK+/- a differential signal, it looks like the terminals are still referenced to ground. See table below from datasheet:

So with 100 ohm differential termination, the low level input is out of spec. (Vil-se max is 0.99V on datasheet, but from you waveform it is a little over 1V) This would explain the unbalanced output you see on PCI-Clock. All of your other waveforms where you were able to successfully generate the PCI-Clock have the REFCLK inputs within the single-ended  h/l and differential pk-pk specification. So visually, the REFCLK levels for 100 ohm differential termination for this device would result in the PCI-Clock output in the figure below:

So technically there kind of is a DC common mode limitation. Please let me know your opinion of this explanation.

Regards,

I.K.

I.K.,

I agree that it looks like a dc common voltage limitation. But is seems as if this common mode limitation also has a correlation with the differential voltage swing.

And why is this limitation not listed in the datasheet?

Regards, Niels

I.K.,

I think that there is a correlation between differential voltage swing and commoon mode voltage, because the clock input works at 1250mV DC common mode voltage when the differential voltage swing is 1200mV. With 800mV differential voltage swing and 1250mV DC common mode voltage, the clock input fails.

But with a common mode voltage below 850mV, the clock input works with a differential voltage swings as low as 300mV.

Regards, Niels

Dear I.K.,

I'm sorry but I can't change the PCI-Clock to 25MHz because there is no way to access PCLK66_SEL.
It is an inner ball of the BGA package and has no connections on our PCB since we rely on the internal pullup.

Regards, Niels