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DP83867IR: DP83867 Power Sequencing

Part Number: DP83867IR

Hello

Thank you for taking the time to answer the following question.

I'm looking to use the DP83867 in a Xilinx Zynq Ultrascale+ design.  Actually been looking at the Avnet UltraZed design and it uses the DP83867 as its Ethernet PHY.  Now looking at the Avnet Design and reading your datasheet and talking to the Avnet ZedBoard forum they recommend this question to you.

In section 10 of the datasheet it shows the 3 supply power configuration and then lists the power supply ramp conditions in regard to the 1.8V and the 2.5V.  The 1.8V must be stable within 25ms of the 2.5V but then there is a curious note about this only applies if the 2.5V is used to power other devices up also.  Why does this matter?  Also it looks like the Avnet design does not follow this and they stated this was not on the original datasheet when they designed it.

So can you please answer if this is a requirement that the 1.8V be brought up with 25mS of the 2.5V.  What would happen if the 1.8V comes first before the 2.5V?  And why does it matter if the 2.5V supplies the DP83867 only or other devices too?

Thank you for you help

Gary

Reference zedboard.com/.../ultrazed-ethernet-dp83867-power-question