Hello,
We are using DS125DF410 to deliver the high speed signals from 10G SFP+ to FPGA, now we are not sure about how to configure the registers, and here is our configuraion below, could you please share your comments on this? thanks.
write_iic_data(0xff,0x0d);//Write all channels
write_iic_data(0x36,0x31);//with a 25Mhz reference clock
write_iic_data(0x2f,0xf6);//Ethernet 10.3125G
write_iic_data(0x60,0x00);
write_iic_data(0x61,0xb2);
write_iic_data(0x62,0x90);
write_iic_data(0x63,0xb3);
write_iic_data(0x64,0xff);
write_iic_data(0x0a,0x10);//Assert CDR reset
or
write_iic_data(0xff,0x0d);//Write all channels
write_iic_data(0x36,0x31);//with a 25Mhz reference clock
write_iic_data(0x2f,0xC6);//Ethernet 10.3125G
write_iic_data(0x60,0x90);
write_iic_data(0x61,0xb3);
write_iic_data(0x62,0x90);
write_iic_data(0x63,0xb3);
write_iic_data(0x64,0xff);
write_iic_data(0x0a,0x10);//Assert CDR reset
write_iic_data(&Iic_device,DF410_ADDR,0x31,0x00);//mode0,adapt CTLE until lock,then DFE, then EQ until optimal
write_iic_data(&Iic_device,DF410_ADDR,0x1e,0x29);//retimer data
write_iic_data(&Iic_device,DF410_ADDR,0x3a,0xc5);//CTLE:EQ
write_iic_data(&Iic_device,DF410_ADDR,0x03,0xc5);
write_iic_data(&Iic_device,DF410_ADDR,0x45,0xc5);
write_iic_data(&Iic_device,DF410_ADDR,0x15,0x30);//Set DEM value
write_iic_data(&Iic_device,DF410_ADDR,0x2d,0x30);//Set VOD value
