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DP83867E: PHY RX_ER Counter clarification

Tomas Galbicka
Prodigy 30 points
Part Number: DP83867E

Hello,

We are using TI Ethernet PHY DP83867E on own board to connect to Ethernet switch in FPGA and I would like some clarification what 

error are exactly capture by Receiver Error Counter Register (RECR), Address 0x0015?

After the board power up, it happens to us that on some boards we are getting CRC errors in Ethernet switch counters and also we can

see that this Receiver Error Counter is also incremented.

This happens occasionally lets say on around 5-10 % from all boards power ups

What errors are capture by this counter?

And from what direction does this Receiver Error Counter capture error?

Is it from RX of MAC side, or RX side of physical CAT-5 cable from point of view of PHY?

When we restart autoneg in register 0x0, we are no longer getting any CRC errors and also Receiver Error Counter is not incremented.

Would you have any idea or tips what could cause following problems?

Thank you,

BR,

Tomas

  • 0
    TI__Mastermind 26320 points

    Hi,

    RX_ER is defined in IEEE802.3u. 

    There are a few things that will trigger RX_ER:
    1. PMD Error
    2. PCS Error

    Opcode violation, DC balance issue, SSD/ESD violation, If the layout of the analog side is poor, it could eat into the margins and cause poor performance at longer cable distances.

    How you are connecting between FPGA and Phy ? Share your schematics and layout for me to look in.

    Regards,
    Geet