Hello
we are designing a latency-sensitive application which is based on precise trigger generation on multiple remote boards. For this purpose we would like to establish a gigabit link between the boards and use the recovered clock on the slave to synchronize the devices. We are targeting jitter-free transmission as well as low and deterministic latency. All triggers must be output within a desired window of 8 nanoseconds. For this purpose we are interested in the DP83867CS IC from TI. The PHY will be connected via SGMII to a Xilinx Artix7 FPGA.
We have some questions:
1. what is the SGMII latency? I found a locked thread on this topic but no measurements have been released by TI. Can you please inform me if any tests have been done and what the MIN MAX latency was found to be.
2. Because we are interested in a trigger jitter of equal or less than 8 nanoseconds it is crucial how the relevant reference clocks are refer to each other. That is why I would like to know what is the relationship between the DP83867CS "local reference clock, the Ethernet transmit clock, and the Ethernet receive clock" mentioned in section 8.3.3 "Clock Output" of the datasheet. Which clocks are derived from the 25MHz oscillator and how are they related to the SGMII recovered clock, extracted from the FPGA data stream towards the TI PHY?
Thank you in advance.
Regards
Valentin
