Hi,
My customer is using the DP83867IRRGZ Gigabit Ethernet PHY connected to the RGMII port of an OcteonTX CN8020 processor. It is working just fine as far as we can tell.
Our concern is the PHY CLK_OUT signal that I am using to drive the processor RGM_REF_CLK reference clock input. The OcteonTX provides the specifications shown below. I cannot find any specifications for the PHY output clock in the TI data sheet.
OcteonTX RGMII Reference Clock Specifications
Frequency = 125MHz
Frequency Tolerance = +/-150ppm
Duty Cycle = 45/55
Period Jitter (peak to peak) = 100ps
Edge Rate (10% to 90% and 90% to 10%) = 2ns
Thank you,
Ryan B.
