Hi all,
I'm using the TLK10232 in a 1 to 1 mode, with 156.25 MHz Refclk and 3.125Gbps Data Rate.
I used the Bring Up Procedures (v.2) PDF to initialize the device (p. 21).
When reading the 1E, F register ("CHANNEL_STATUS_1") I see that the 6th bit is always high, indicating that the an overflow has occurred in the transmit data path (CTC) FIFO.
This happens when either sending K28.5 or data.
The LS side is connected to a CYCLONE (ALTERA) FPGA's transceivers and using the same data rate and the same reference clock.
The transceivers in the FPGA encode and decode the data to the 8b/10b form (as in the 1:1 mode, this is not done in the TLK10232).
We see that some of the packets are sent OK but a lot of the time we see that we receive a "9C" symbol (K28.4), maybe indicating an error in the system, maybe the overflow that we see in the "CHANNEL_STATUS_1" register.
What might be wrong with this setup?
Are there any configurations that are needed, in addition to those that are described in the Bring Up Procedures (v.2) PDF?