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DS90UB954-Q1: Communication timing setting register of CSI-2

Part Number: DS90UB954-Q1

Hi team,

Our customer has a problem that communication error due to buffer overflow.

953 CSI-2 input is 800 Mbps, 954 CSI-2 output setting is also 800 Mbps.

They say that after adjusting 0×44 to 0×48 of the indirect register, buffer overflow disappeared and HS mode data transfer was possible.
Could you teach me the role of these registers.
 0x44:CSI0_THS_PREP
 0x45:CSI0_THS_ZERO
 0x46:CSI0_THS_TRAIL
 0x47:CSI0_THS_EXIT
 0x48:CSI0_TPLX
In LP mode, the CSI-2 pulse width of 954 is more wide than input of 953.
Is there a setting for pulse width in LP mode?
Best regards,
Tomoaki Yoshida
  • Hi Yoshida-san,

    Buffer overflow means your input rate is faster than your output rate.

    Indirect registers 0x44-0x48 controls your CSI timing. By adjusting those values, you are changing the CSI timing to allow for more data to be sampled in HS mode.

    The figure below shows the timing parameters these registers are changing:

    Best,

    Jiashow

  • Hello Tomoaki

    Our customer is facing the overflow of CSI-2 that same as you.
    Did your customer fix it? Do you know how to fix it?

    Regards,
    Nao
  • Hi Nao,

    Have you tried the suggestions I recommended above?

    Best,
    Jiashow
  • Hi, Jiashow

    Thank you for your reply.
    Our customer tried to change this register.
    They changed that all register value are minimum.
    And then, Their system works without the buffer overflow.
    BUT, AC timing does not meet CSI-2 spec.

    So, do you have any advice of each register settings?

    Regards,
    Nao
  • Hi Nao,

    Is it possible for them to run their imager at a slow frame rate? This is the easiest way to resolve buffer overflow.

    Best,
    Jiashow
  • Hi, Jiashow

    No... I guess their system is fixed date rate.
    Do you have any idea?

    Regards,
    Nao
  • Hi Nao,

    Could you provide more details of their system? What imager are they using? What's the frame rate? Bits per pixel?

    Best,
    Jiashow
  • Hi, Jiashow

    Their system is NOT using popular imager.
    They use IC which has CSI-2 I/F and details are an undisclosed.

    Other their system information.
    1. The frame rate is 7kpbs.
    2. Bits per pixel is 800Mbps/lane (They use 4 lane.)

    Regards,
    Nao
  • Hi Jiashow-san,

    Our customers have not solved this issue yet.
    According to their analysis, the CSI-2 output timing in LP mode is different from the input and becomes slow.
    For example, the input LP-11 state is 200 ns, but the output it is very long, 600ns.
    Packet transmission time in HS mode is the same as input.
    The output timing gradually delays for each LP mode, so it seems that buffer overflow will eventually occur.

    They think that timing adjustment like MR_TCK_PREP is not optimal automatically.
    Should user usually adjust these registers?

    Best regards,
    Tomoaki Yoshida
  • Hi Yoshida-san,

    Typically customers don't need to adjust these registers.

    What's your input CSI data rate per lane and your output CSI data rate (in reg 0x1F). The reason why the LP timing is different could be because of different CSI rate.

    Best,
    Jiashow
  • Hi, Jiashow

    Do you have any update for my information?
    Should I rise new thread?

    Regards,
    Nao
  • Hi, Jiashow

    Our customer issues is as same as Tomoaki's case.
    > For example, the input LP-11 state is 200 ns, but the output it is very long, 600ns.

    Hence, our customer tried to change the 0x47(=CSI0_THS_EXIT) register on UB954.
    BTW, LP-11(idle time) does not change in this register value.

    How do we change the LP-11 value?

    Regards,
    Nao
  • Hi Nao,

    The reason why your LP-11 timing is different is because the output is running at a different rate than your input. Our 954 deserializer outputs CSI data at a fixed rate that isn't always the same as the input rate. You don't want to change the LP-11 value because the LP-11 timing is already correct for the specified CSI rate.

    Refer to section 7.4.21 in the datasheet for more information:

  • Hi, Jiashow

    Thank you for your quick reply.
    System requirement of our customer is "Bits per pixel is 800Mbps/lane (They use 4 lane.)".
    And CSI_PLL_CTL(0x1F) value is 0x02.
    I guess CSI-2 timing is same if I believe our customer's comment.

    Please let me know if I need to check other registers.

    Regards,
    Nao
  • Hi Nao,

    Just to clarify, the customer only has one sensor right? The CSI output is not aggregated. Could you verify the input and output timing again because it should be consistent if the data rates are the same.

    Best,
    Jiashow
  • Hi, Jiashow

    Yes. My customer is using one sensor.

    Here is packet waveform of my customer system.
    The yellow is CSI input data of UB953).
    The blue is CSI output data of UB954.

    Data bit timing is almost same. (560ns)
    But, Idle timing is difference. Input data is 240ns. Output data is 600ns.
    Our customer want to know how to fix it?
    Do you have any ideas?

    Regards,
    Nao

  • Hi Nao,

    Are you seeing any errors other than buffer overflow?

    Could you zoom-in on your input side to provide the timing relationship LP-11, LP-01, LP-00, HS transition and make sure they meet the CSI spec?

    Also, could you zoom-out to show multiple frame blankings?

    Thanks,
    Jiashow
  • Hi, Jiashow

    This is zoom-out waveform.
    Could you check it? Please tell me the comment.

    I will ask my customer about #1 and #2 question.
    #1 Are you seeing any errors other than buffer overflow?
         - Please tell me the address of registers to check  just in case.
    #2 Could you zoom-in on your input side to provide the timing relationship LP-11, LP-01, LP-00, HS transition and make sure they meet the CSI spec?

    Regards,
    Nao

  • Hi Nao,

    From the deserializer could you check registers 0x54-0x57 for any errors?

    From the serializer could you check registers 0x5C-0x64?
  • Hi, Jiashow

    Thank you for your update.
    I asked our customer it. Please wait.

    Please let me check again.
    Is there a way to change the value of LP - 11?

    Regards,
    Nao
  • Hi, Jiashow

    Do you have any update about this?

    >Is there a way to change the value of LP-11?

    Regards,
    Nao
  • Hi Nao,

    There's no register where you can change the timing of LP-11. Could you provide the registers and values the customers are setting? (for example, are they only forwarding one port to the CSI?)

    Best,
    Jiashow
  • Hi, Jiashow

    Thank you for your update.

    There are some error in register 0x5C-0x64 of UH953.
    Our customer is confirming this error now.
    I will get back to you, if I get new information.

    One more thing, I will ask our customer that I can send you their register value.

    Regards,
    Nao
  • Hi Nao,

    Has customer gotten back to you regarding this issue?

    Best,
    Jiashow
  • Hi, Jiashow

    UH953 system is developing other customer.
    So, my customer currently inquiring with other customer.
    I will tell you soon if I get reprocess of our customer.

    Regards,
    Nao