DS90UB948-Q1: DS90UB948-Q1 internal pattern generator

Hello,

Does the 948 stop responding after a certain command in your code or just after any access at all to the indirect registers? 

Best Regards,
Casey 

It stops responding after writing in PGID (data) register. First time when I write data in PGID register the deserialiser sends ACK but after that it stops. I can write PGIA (address) register many times without ACK fail. So, after writing the PGID register it stops working.

*So, after writing the PGID register with any value it stops working.

Hello,

This behavior doesn't match anything we have seen. Can you please send over the register writes you are programming?

Best Regards,

Casey 

http://www.ti.com/lit/an/snla132d/snla132d.pdf

For instance: I want to follow the 4.3 chapter (Configuration Sequence) from this application note. 

a. Write 0x03 (Table 5) to address 0x66 PGIA (Table 5) to enable PGCDC1, then write 0x06 (Table 12) to address 0x67 PGID (Table 5) to set the clock divider to be 6 (200/33.3). -> When I write 0x03 in PGIA it works, when I write in PGID it works -> AFTER PGID write everything fail to ACK. 

b. Write 0x07 (Table 5) to address 0x66 PGIA (Table 5) to enable PGAFS1, then write 0x20 (Table 16) to address 0x67 PGID (Table 5) to set desired Active Horizontal Width. - FAIL (c,d,e and so on). 

It fails only when I write PGID register. If I skip writing the data register I can write for many times in PGIA register.

Hello,

It sounds like the issue may be from the I2C controller rather than the 948 device. I just sanity checked by doing your above steps on the EVM for 948 with no deserializer connected:

Write 0x03 to 0x66

Write 0x06 to 0x67 

After this I am still able to read and write all registers properly. We have not had any complaints of this behavior before with this device either. 

Best Regards,
Casey 

Ok. After I write 0x06 to 0x67 address (PGID) I got an ACK but after that no command can be sent anymore. :(

Hello,

Are you testing using the EVM module or some sort of custom design?

Thanks,

Casey 

It is a custom design.

Hello,

I would suggest verifying performance with our EVM device if possible. The only other thing I could think besides the problem being from the I2C master configuration is a problem with the device power up sequence. Please ensure the power up sequence of the rails and PDB signal match the 948 datasheet section 9.1

Best Regards,
Casey 

Hello,

Were you able to test with the TI EVM? Did it give the correct I2C behavior? Or were you able to trace any other issue here?

Best Regards,

Casey