Hi,
In DP83640 Datasheet, COL pin is defined as PHY Address 0 strap pin and stated that it is internally pull-up. We have left this pin float in our design. With this design, when we check PHY addresses from our u-boot, we see that the address for this PHY is 0. When we PHY registers it is also read as 0.
Moreever, when we read 0x00 register it returns 0x3100, means PHY is not in isolate mode. In the datasheet, it is stated that a PHY Address of 0 puts the parts into the MII Isolate Mode.
Let me say that in our u-boot (as response to "mdio list" command), this PHY is seen as "generic PHY" while DP83867 is seen "TI DP83867".
Regards,
