Hi team,
my customer are using TUSB564 in their design and would like to clarify the following:
1. When TUSB564 is switched to 4 Lane DP (pin assignment C), does teh downstream SSTXp/SSTXn pair still do RX.term detection? or it will be disabled?
2. In I2C mode, is there any latency or overlap when switching between USB3.1 only, or 2L/4L DP mode? Datasheet only mentioned transition requirement in GPIO mode but not in I2C mode.
3. When hold and re-enable the device EN pin of TUSB564, is the timing shown in table 8 (power up timing), tcfg_su, tcfg_hd and tctl_db still applied?
Regards,
SK Loo