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TUSB564: 2 lane and 4 lane DP switching

Part Number: TUSB564

Hi team,

my customer are using TUSB564 in their design and would like to clarify the following:

1. When TUSB564 is switched to 4 Lane DP (pin assignment C), does teh downstream SSTXp/SSTXn pair still do RX.term detection? or it will be disabled?

2. In I2C mode, is there any latency or overlap when switching between USB3.1 only, or 2L/4L DP mode? Datasheet only mentioned transition requirement in GPIO mode but not in I2C mode.

3. When hold and re-enable the device EN pin of TUSB564, is the timing shown in table 8 (power up timing), tcfg_su, tcfg_hd and tctl_db still applied?

Regards,

SK Loo

  • SK

    1. When TUSB564 is switched to 4 Lane DP (pin assignment C), does teh downstream SSTXp/SSTXn pair still do RX.term detection? or it will be disabled?

    The USB RX.TERM detection will be turned off when TUSB564 is in 4 lane DP mode.

    2. In I2C mode, is there any latency or overlap when switching between USB3.1 only, or 2L/4L DP mode? Datasheet only mentioned transition requirement in GPIO mode but not in I2C mode.

    In I2C mode, there is no overlap. 

    3. When hold and re-enable the device EN pin of TUSB564, is the timing shown in table 8 (power up timing), tcfg_su, tcfg_hd and tctl_db still applied?

    No, the timing at Table 8 only applies to FLIP, CTL[0:1], I2C_EN, EQ, SSEQ, and DPEQ.

    Thanks

    David

  • Thanks David,

    In this case, what will be the timing for tcfg_su, tcfg_hd and tctl_db during re-enabled?

    When the TUSB564 is disabled via EN, can the I2C still work?

    What it the condition for TUSB564 to enter U2/U3 when in USB 3.1 mode?

    Regards,

    SK Loo

  • SK 

    Are you in GPIO or I2C mode? Please note device disable function is not used when in I2C mode.

    I2C will still work when TUSB564 is disabled via EN. 

    Because the TUSB564 is a linear redriver, it can’t decode USB3.1 physical layer traffic. The TUSB564 monitors the actual physical layer conditions like receiver termination, electrical idle, LFPS, and SuperSpeed signaling rate to determine the USB power state of the USB 3.1 interface.

    Thanks

    David