Inconsistent datasheet information DS100DF410

Hi Tiguru

We are looking into your question, our AE will provide a reply later today.

regards,

TK Chin

Hi,

   Thanks for your assistance.  I have a few more questions regarding the datasheet.  Here's what I need help with:

1. We want to power up the channel in the absence of input signal to use PRBS.

P. 29 tells us to power set bit 7 and clear bit 6 of register 0x14. If there is signal, it tells us to clear both bit 7 and bit 6. What is the function of bit 6? It is abbreviated "eq_sd_reset" but described as "Force Signal Detect Off". Is it reset or of static off? A description of the bit 6 function and use would be very helpful.

2. "Resetting Individual Channels of the Retimer" on p.26 tell us to "...When bit 2 [of register 0x0a] is subsequently cleared...". Does it have to be explicitly cleared or is it a self-clearing bit?

3. "Overriding the VCO Divider Selection" on p.29. Is there any description on how the ratio relates to the output frequencies? We are enabling the PRBS generator with no input signal.

4. "Using the PRBS Generator" on p.30 it says:

First write a 1 to bit 3 of register 0x09, then 0x0 to bits 1:0 of register 0x1b. This disables the charge pump for the phase-locked loop.

In Table 5 there is no bit 3 in the description of register 9. There is no description of register 0x1b.

Same page:

Now write a 1 to bit 6 of register 0x09.

In Table 5 there is no bit 6 in the description of register 9.

Same page:

Once the LPF DAC is enabled, write the desired value of the LPF DAC output in register 0x1f, bits 4:0.

Bits in register 0x1f is shown as "Select Output Polarity Inverted" - what is the correct register to use?

5. "Using the Internal Eye Opening Monitor"

On p.31: reinstating HEO and VEO values should be performed once the eye has been acquired. What is the indicator of eye acquisition completion?

On p.32:

Register 0x22, bit 7, the eom_ov bit, should be cleared in this mode.

In Table 5 there is no register 0x22.

The eye monitor collects a matrix of 64 x 64 phase / voltage measurements. What is the order of phase/voltage in sequence of reading it from the registers 0x25 ( and 0x26) - what is rows and what is columns? Do the start from the center, the go up or down right or left?

Register 0x2a sets accumulation time. At its maximum value of 0xff this is 2**18 samples. That is pretty long time even at tens of gigasamples/second. What happens to the values during sampling - are they averaged? are they reset? What happens when the sampling period ends - does the counter(?) stops or rolls over? How does one know that the sampling period ended?

6. "Overriding DFE Taps and Polarities"

p. 33: are the DFE observation registers 0x71 through 0x75 constantly updated even when the DFE is powered down?

The starting DFE weights may be updated - what are the starting tap weights, the manually loaded ones or the observation ones?

Is the DFE powered down even when the DFE adaptation is selected through the adaptation algorithms in Table 11? Does the DFE have to be always explicitly powered up through bit 3 of register 0x1e?

7. "Initiating Adaptation"

On p. 35 it says:

DFE adaptation can be initiated by setting and then clearing bit 2 of register 0x24.

Table 5, however, shows this bit as self-clearing - which one is correct? Similar bit for the CTLE, bit 0 of register 0x2f - is it self-clearing or not? What is the condition of self-clearing?

8. "Setting the Reference Enable Mode"

 On p. 35:

Register 0x36, bits 5:4, are the ref_mode<1:0> bits. These bits should be set to a value of 2'b11. Note that this is not the default.

The Table 5, however, shows that 2'b11 is the default for these bits - which part is correct?

9. General question:

What is the protocol for sending the register address over the SMBus - sending device address, Read/Write, and data is well understood - but when and in what sequence is the register address send both for the individual and block access?

10. Considering a few of the above questions, is there an errata document?

In advance, thank you for your help.

Hi,

Sorry for the missing register information on the DS100DF410 datasheet. We are working on updating this document to ensure capturing a basic definition and description of every bit of every channel register. In the meantime, I can provide feedback on the registers/bits you have called out:

1.  Bit 3 of register 0x09. Table 5 does not show this bit.

• This bit is the enable bit for override of the phase detector and frequency detector charge pump enable bits (pd_fd_cp and pd_pd_cp) values with the value in register 0x1B[1:0]

• Bits 1:0 of register 0x1b. There is no such register in Table 5.

• bit 1 -> enable bit for phase detector charge pump (CP_EN_CP_PD), value is '1' for normal operation
• bit 0 -> enable bit for frequency detector charge pump (CP_EN_CP_FD), value is '1' for normal operation

• Bit 6 of register 0x09. Table 5 does not show this bit.

• Enable bit to override lpf_dac_val with value in register 0x1F[4:0]

• Bits 4:0 of register 0x1f. There are no such bits in register 0x1f in Table 5. It may be register 0x0b - just a guess.
  • lpf_dac_val[4:0] -> 5 bits to set low pass filter DAC value

Cordially,

Rodrigo Natal

DPS Applications Engineer

Hi.

With respect to the ten items in your latest post where assistance is needed, I need some time to review and generate responses. I should be able to reply within 1-2 days.

Cordially,

Rodrigo Natal

Thank you very much for your help Rodrigo!  It is greatly appreciated.

Regards,

TIG

Hi. See below related to your questions.

1. We want to power up the channel in the absence of input signal to use PRBS. P. 29 tells us to power set bit 7 and clear bit 6 of register 0x14. If there is signal, it tells us to clear both bit 7 and bit 6. What is the function of bit 6? It is abbreviated "eq_sd_reset" but described as "Force Signal Detect Off". Is it reset or of static off? A description of the bit 6 function and use would be very helpful.

Below are the descriptions of 0x14 bits 7 and 6.

These bits are both Read/Write and are static, not self-clearing

2. "Resetting Individual Channels of the Retimer" on p.26 tell us to "...When bit 2 [of register 0x0a] is subsequently cleared...". Does it have to be explicitly cleared or is it a self-clearing bit?

This bit needs to be cleared, it is not self-clearing.

 3. "Overriding the VCO Divider Selection" on p.29. Is there any description on how the ratio relates to the output frequencies? We are enabling the PRBS generator with no input signal.

The default DS100DF410 VCO frequency is 10.3125GHz. When in free mode and with divider ratio of 1, the resulting output data rate should be near 10.3125G. Data rates at other divider settings would be multiples of it

4.  Channel Registers 0x09, 0x1B, 0x1F

See descriptions below:

0x1F bit 7 when asserted selects Output Polarity inverted.

5. "Using the Internal Eye Opening Monitor" On p.31: reinstating HEO and VEO values should be performed once the eye has been acquired. What is the indicator of eye acquisition completion?

The data from the eye opening monitor is available as quickly as it can be read over the SMBus. When all the data has been read, the DS100DF410 clears the eom_start bit.

On p.32: Register 0x22, bit 7, the eom_ov bit, should be cleared in this mode.In Table 5 there is no register 0x22.

See below

The eye monitor collects a matrix of 64 x 64 phase / voltage measurements. What is the order of phase/voltage in sequence of reading it from the registers 0x25 ( and 0x26) - what is rows and what is columns? Do the start from the center, the go up or down right or left?

The data recorded from the Eye Opening Monitor (EOM) begins at (X, Y) position (0, 0) and proceeds to

position (0, 63). Next, the Y-value is reset to 0 and the X-value is incremented. This process is repeated

until the entire 64 x 64 matrix is read out

Register 0x2a sets accumulation time. At its maximum value of 0xff this is 2**18 samples. That is pretty long time even at tens of gigasamples/second. What happens to the values during sampling - are they averaged? are they reset? What happens when the sampling period ends - does the counter(?) stops or rolls over? How does one know that the sampling period ended?

The data from the eye opening monitor is available as quickly as it can be read over the SMBus. When all the data has been read, the DS100DF410 clears the eom_start bit.

See below register description for 0x2A.

6. "Overriding DFE Taps and Polarities" p. 33: are the DFE observation registers 0x71 through 0x75 constantly updated even when the DFE is powered down?

No.

The starting DFE weights may be updated - what are the starting tap weights, the manually loaded ones or the observation ones?

 The manually loaded ones.

Is the DFE powered down even when the DFE adaptation is selected through the adaptation algorithms in Table 11? Does the DFE have to be always explicitly powered up through bit 3 of register 0x1e?

Yes, you must always power up the DFE via write to 0x1E.

7. "Initiating Adaptation" On p. 35 it says:  DFE adaptation can be initiated by setting and then clearing bit 2 of register 0x24. Table 5, however, shows this bit as self-clearing - which one is correct? Similar bit for the CTLE, bit 0 of register 0x2f - is it self-clearing or not? What is the condition of self-clearing?

See 0x24 register description below. Bit 2 is self-clearing after user sets it to ‘1’.

See description below for register 0x2F:

8. "Setting the Reference Enable Mode"On p. 35: Register 0x36, bits 5:4, are the ref_mode<1:0> bits. These bits should be set to a value of 2'b11. Note that this is not the default. The Table 5, however, shows that 2'b11 is the default for these bits - which part is correct?

See below register 0x36 description ( the third column from the left is the bit default value)

9.General question: What is the protocol for sending the register address over the SMBus - sending device address, Read/Write, and data is well understood - but when and in what sequence is the register address send both for the individual and block access?

Protocol is same as I2C. A sequential write is initiated the same way as a single byte write, but the host master does not send a stop condition after the first word is clocked in. The slave sends an acknowledge after each data word is received. The host must then terminate the sequential write sequence with a STOP condition.

10. Considering a few of the above questions, is there an errata document?

We are currently working on a datasheet upgrade to capture all registers and provide more detail on retimer configuration.

Cordially,

Rodrigo Natal

DPS Applications Engineer

Rodrigo,

Thank you for the answers - very helpful. I would appreciate some clarifications. I've listed them in the same order related to the original questions.

Hi Ben, see below:

1. Thank you for the meaning and action of the bits 7 and 6 of 0x14. Under what scenario would we ever want to set bit 6 of register 0x14 (it always seems to be cleared)?

It is one way to disable a channel. Such operation might be useful during system testing or debug.

3. If the VCO divider selection is a straight divide then "divide by 16" gets us 0.645GHz bit rate. Does the IC go that low? As a matter of fact, I did not see any mention of the lower supported bit rate limit in the datasheet.

No. The CDR may not lock for all divider and data rate combinations.

5. Register 0x22 understood - thank you. As for the 64x64 array - yes, it goes first X and then Y.

First question: what is X - voltage or phase?

 Phase

Second question: Where is the starting point of voltage and of phase from the center of the eye? If (X, Y) is (0, 0), the what part of the eye is that - center, upper left corner, or where?

Lower left corner

I am still pretty confused about the accumulation time in register 0x2a even after the new register bit field description:

The counter is a 16 bit counter but we see only the top 8 bits of the counter in register 0x2a - correct? The counter counts in 32-bit words - don't get it, do you mean 32 counts (2**5)? Please, explain.Therefore, the total number of bits is 32 times this value - that may explain the above. So the granularity of the time setting for the counter is 32 * 2**8 (lower byte of the counter that we don't see) = 2**13 - correct? How often does the sampling occur - how do we convert it into time or UIs?

Either way, I cannot convert any of the above numbers to the 2**18. Maybe, instead of me guessing, another explanation would be very helpful.

Please note below on register 0x2A time conversion:

32* TVCO * reg 0x2A * 256 = time spent on each point

For example:

-              10.3125Gbps operation

-              Reg 0x2A = 0x30

-              Then the time spent on each point = 32 * 96.9697ps * 48 *256 = 38.13 us (default setting)

9. The answer refers to "block write". The question is related to the register address. The I2C (or point me to the right place, please) talks about sending first the address and then the data (in the case of a single byte write; same for read). However, the IC has two levels of addressing - the address of the device (7-bit) and the address of the register. When and how is the register address sent? Between the device address and the data? Details?

A register write is accomplished when the host/controller sends a START condition on the SMBus followed by the Write address of the DS100DF410 device to be configured. After sending the Write address of the DS100DF410, the host/controller sends the register address byte followed by the register data byte. The DS100DF410 acknowledges each byte written according to the data link protocol of the SMBus Version 2.0 Specification. See this specification for additional information on the operation of the SMBus.

11. In your response there is a more detailed description of register 0x09. In that register there is new bit 1 "PD_FLD_OV" with the following description: "Enable to override pd_fld with value in reg 0x1E[1]" What is "pd_fld"? I take it, it is PowerDown something... How do you use it? There is no bit 1 in register 0x1e.

FLD stands for “false lock detection.” The DS100DF410 implements a false lock detection circuit to ensure the CDR does not lock to incorrect frequency harmonic. Register 1E bit 1 enables you to disable false lock detection if the register 0x09 override bit is enabled.

Cordially,

Rodrigo Natal

DPS Applications Engineer

Rodrigo,

Thank you for the answers - all pretty clear.

A few more questions:

1. Would be great to get a complete description of register 0x1e.

2. For the DFE tap polarity in registers 0x71 through 0x75 - is "1" positive or negative?

3. This must be a typo - p.33 lists DFE tap polarity as negative with default "0" whereas the table shows the default as "0" (bit 7 or register 0x12). Which one is correct?

4. Now a pretty important question: the datasheet lists the part as operating at two fixed rates: 10.3125Gbps and 1.25Gbps. Nevertheless, there are VCO and other frequency controls. Is it possible to run it at other rates, e.g. 2.5Gbps? What would the setting be, roughly?

Thank you very much for your support,

Ben

1. See below for register 0x1e

2. "1" means negative DFE tap polarity

3. The DFE polarity default value (as indicated on the corresponding bit from registers 71-75) for all taps is "0". The register 0x12 value (for forcing DFE tap 1 polarity) only applies when you are in manual programming mode i.e. Adapt Mode 0. 

4. The DS100DF410 is only intended to support the Ethernet rates (10.3125Gbps and 1.25Gbps.) For multi-rate support we have the DS110DF410 and DS125DF410 part numbers.

Cordially,

Rodrigo Natal

DPS Applications Engineer

Rodrigo,

Thank you very much.

Ben