DS90UB913/914 seems to bit-shift the bus

Vivek Sikri

Hello TI Experts,

As a test of my LVDS link I am sending a 4 bit counter to the DS90UB913Q (On D[9:6]) which I then expect to see on the same data bit outputs of the DS90UB914Q that the serializer is connected to. The strange thing is that I see the bits coming out but shifted by 1.

To illustrate my point:
D9 pin - Serializer has a 750KHz signal going into the pin - Deserializer has a 1.5MHz signal coming out
D8 pin - Serializer has a 1.5MHz signal going into the pin - Deserializer has a 3MHz signal coming out
D7 pin - Serializer has a 3MHz signal going into the pin - Deserializer has a 6MHz signal coming out
D6 pin - Serializer has a 6MHz signal going into the pin - Deserializer has nothing coming out, just stays low

So what goes in to bit N seems to come out of bit N+1.

The reason I'm using only four pins is that the sensor is a very low resolution thermal sensor (80x60 pixels) and has a serial output not parallel. I'm essentially sending the single serial bit over the link, and just added a few bits for other signals in case I need them. This SerDes chipset is arguably overkill for this application but it made sense to use it since I already have a Deserializer board with everything else I need on there. In essence I only needed to build a new serializer+sensor board. I wanted this new sensor board to plug into the same port as my old sensor board using this chipset, so I went this route.

Here's a summary of my setup:

FPGA <---- DeSer <----------> Ser <---- CPLD <----- Thermal sensor

The CPLD is used to get the data out of the thermal sensor as we need something to generate H/V sync for the Serializer, and to drive the clock to the sensor to get data out. At this stage the sensor isn't really involved, I'm just generating the counter in the CPLD and sending it along with H/V and PCLK signals.

For PCB routing ease on what is a pretty small board I hooked up to the most convenient to route four data pins and connected the rest of the bus to ground. So in this case I'm using D9:6 and have connected D11, D10 and D5:0 to ground.

I'm in external clock mode with the clock and PCLK both at 12.5MHz. The mode I'm using is 12 bit LF mode so a 1:1 ratio of PCLK:EXTCLK is what is required.

The lock signal out of the deserializer is high and doesn't have any glitches. Running BIST gives no errors.

Any ideas on what might be causing this issue?

Thanks,

Vivek

over 9 years ago

0 Mark Sauerwald88474 over 9 years ago

TI__Genius 13475 points

Vivek
One of the first things that I would do is to verify that the PCLK frequency going in to the DS90UB913A is the same as the PCLK that is being recovered from the 914A.
Also, please note that 12.5MHz is below the minimum speed spec for these products, it is possible to run the device with a faster PCLK?

0 Vivek Sikri over 9 years ago in reply to Mark Sauerwald88474

Intellectual 300 points

Hi Mark,

Thanks for the quick response.

For the DS90UB913A I see that 25MHz is the minimum speed, however for the DS90UB913Q in 12 bit LF mode the datasheet says 10MHz is the minimum speed so 12.5MHz should be OK. That being said I was concerned about running the PCLK at so close to the minimum so I did try 25MHz and just send each bit twice. That also resulted in bit errors though I can't categorically say they were the same errors as what I'm seeing now.

The PCLK coming out of the deserializer is 12.5MHz, same as that going into the serializer.

In addition to the bits being shifted up one I see that the hsync and vsync signals out of the deserializer are stuck low. The Lock signal is going high and not glitching at all (measured with a scope not the Lock LED).

Thanks for your help, I'm really stuck on this one.

Regards,
Vivek

0 Vivek Sikri over 9 years ago in reply to Vivek Sikri

Intellectual 300 points

Hi Mark,

So I went back to 25MHz PCLK and EXTCLK and verified that the bit error behavior is the same.

Thanks,
Vivek

0 Vivek Sikri over 9 years ago in reply to Vivek Sikri

Intellectual 300 points

Hi Mark,

Some more information. I switched over to using PCLK mode to see if that helps the cause. Some luck but not yet working:

* In PCLK mode with a 25MHz PCLK frequency I see that D9:7 are coming through OK. D6 just sits at a static level. I probed the serializer inputs and see that D6 is actually toggling.
* Repeated this with a 12.5MHz PCLK and saw the same thing.
* In both these cases the PCLK coming out of the deserializer is half the frequency of the clock going into the serializer! This makes sense then that D6 would just sit at a static level because D6 toggles at half the speed of PCLK into the serializer (it's the LSB of a 4 bit counter I'm using to generate a test pattern, and the counter runs off PCLK). Since the deserializer is for some reason recovering a clock that is half the speed that it should then it clearly can't put out a data signal at that same speed. D7 and up work fine.

So the question becomes why would the deserializer put out a PCLK that is half the speed of the clock going into the serializer? This is 12 bit LF mode on the deser mode pin, PCLK mode on the serializer mode pin and PCLK frequency of either 25 or 12.5MHz.

Are these symptoms consistent with the clock jitter be too high? I would think if the jitter was too high the link wouldn't Lock.

My clock is sourced from a 25MHz, 10ppm oscillator but through the CPLD. In the case of a 25MHz PCLK it is direct pass through from the CPLD and for the 12.5MHz PCLK it is divided in two by the CPLD. For flexibility I setup the Ext clock also through the CPLD as it is connected to the GPO3 pin. For Ext clock mode I can run either the 25MHz or 12.5MHz clocks to the GPO3 pin. I match the PCLK frequency to whatever is going to the Ext clock pin.

I'm going to try hard-wiring the oscillator directly to the Serializer Ext Clock pin and see if that helps.

Meanwhile any other suggestions would be much appreciated.

Thanks,
Vivek

Interface

Interface forum

DS90UB913/914 seems to bit-shift the bus