8b/10b Serializer and Deserializer Selection

Hi Mickey,

To clarify, does the K-code generation need to be implemented by the serializer, or is the K-code generation coming from a source prior to the serializer, like an ASIC or FPGA? If it is coming from an ASIC/FPGA source, then there are plenty of devices that can be used with this type of data.

For a SerDes chipset, it is also important for us to know the following:

1. What is the bit depth (10 bits, 14 bits, 28 bits) to serialize per clock cycle?

2. What is the operating clock speed?

3. What is the parallel and serial topology requirement? For example, is the parallel LVCMOS or LVDS? Is the serial side LVDS or CML?

4. What is the operating temperature range? Is it consumer (-10 to 70C), industrial (-40 to 85C), etc.?

5. What is the application that this SerDes chipset will be used in? For example, will it be for a backplane application, display application, camera application, etc?

Thanks,

Michael

Hi Michael,

1. There is a communication link, that is the front device A---to---TI Serializer ---to---FPGA. The K-code is generated by the front device A, then the K-code is sent to TI serializer.

2.What is the bit depth (10 bits, 14 bits, 28 bits) to serialize per clock cycle? 10bits or 20bits or 30bits

3.What is the operating clock speed? The clock speed is 62.5MHZ and the data speed is 625MHZ.

4. What is the parallel and serial topology requirement? For example, is the parallel LVCMOS or LVDS? Is the serial side LVDS or CML?
(1). The input is the parallel level and it can be any level for the serializer, for example, LVCMOS, LVDS or any other level can be OK.
The output is the serial LVDS for the serializer.

(2). The input is the serial LVDS for the deserializer. The output is the parallel level and it can be any level for the deserializer, for example, LVCMOS, LVDS or any other level can be OK.

5. What is the operating temperature range? Is it consumer (-10 to 70C), industrial (-40 to 85C), etc.?
Both consumer and industrial are OK.

6. What is the application that this SerDes chipset will be used in? For example, will it be for a backplane application, display application, camera application, etc?
Interior , the medical equipment.

Hi Michael,
Can you see my reply? The customer is waiting for my reply.

Hi Mickey,

It sounds like the SCAN25100 would deserialize the data.  You would need a 31.25 MHz clock to run at the 625.0 MHz datarate.

The SCAN25100 was designed to work with the K28.5 character.  I'm not sure how it will operate using other K-characters.

Regards,

Lee

Hi Mickey,

It looks like the SCAN25100 is able to implement 8B/10B encoding on its own. This device may be suitable for you if you require this built-in functionality, just as Lee suggested.

I am assuming that the data speed you are mentioning is just 10 bits x 62.5 MHz = 625 Mbps. If so, then the parallel speed is actually 62.5 Mbps. Is this correct?

With the assumption that the above is correct, I have a few other suggestions that may be suitable if the SerDes is not responsible for generating the K-code:

1. DS92LV1023E and DS92LV1224 chipset. This chipset supports 10-bit applications from 30-66 MHz. You will need to use a reference clock on the deserializer side in order to achieve lock.

2. DS92LV2421 and DS92LV2422 chipset. This is a Channel Link II chipset that will serialize up to 28 bits LVCMOS to a serial Channel Link II stream, then deserialize back to LVCMOS. No reference clock is required, as the deserializer will lock to the incoming serial data.

3. DS92LV0421 and DS92LV0422 chipset. This is also a Channel Link II chipset and operates similar to the DS92LV2421/22 chipset, but the parallel side consists of 4 OpenLDI LVDS pairs as opposed to 28 bits of LVCMOS data.

Please let me know if any of these solutions is suitable.

Regards,

Michael

Hi Michael,
Your assumption is correct.
The output is CML for DS92LV2421 and DS92LV0421, but the customer's requirement is the serial LVDS for the serializer. The input is CML for DS92LV2422 and DS92LV0422 ,but the customer's requirement is the serial LVDS for the deserializer.

Can only DS92LV1023E and DS92LV1224 meet the customer's requirements?

Hi Mickey,

If your customer strictly requires a 10-bit device that serializes LVCMOS to LVDS and then deserializes LVDS to LVCMOS, then the DS92LV1023E and DS92LV1224 meet these requirements. However, I would like to check about the reasoning that the customer has for LVDs specifically on the serial stream. If TI provides both the choice of the serializer and deserializer, I don't see an issue with using CML as the topology between the serializer and deserializer. Can you clarify the customer's concern with using CML between the serializer and deserializer?

Thanks,

Michael