DS32EL0124/0421

Hello Michael,

attached the schematic.

Best regards

Egon

Hello Michael,

I talked to the customer. He did not use our DS32EL0421 as transmitter !

die input signal is generated from an optical to electronical converter (SFP Modul Avago AFBR-57R5AEZ). (sfp.png)

followed from a Gbit Crosspoint Switch (gbsw.png) and finally to our DS32EL0124.

 the customer try to reset the high-speed channel using the reset signal Reg[0x20] (Device Config) but also this do not work.

Best regards

EgonNB4N840M-D.pdfDS_AFBR-57R5AEZ_29Jan20130.pdf

Hi Egon,

Thanks for the schematics and datasheets. These are helpful.

It looks like RS_B = High and DC_B = Low, so Remote Sense is disabled and DC-Balance is enabled. This allows the DS32EL0124 to be used with any transmitter, so long as the transmitter encodes data in the same way that the DS32EL0421 does and is AC coupled. From the schematic, I can see the AC coupling at the output of the AFBR transceiver, and the DS32EL0124 schematic looks correct.

Would you be able to get some more information about the transmitter and how the transmitter works, since they are not using the DS32EL0421?

For example, it is important to keep the TXIN4 parallel input (Data Valid Input) to the transmitter high for 110 LVDS clock periods to allow the deserializer to lock properly. Also, it would be good for us to know whether any signal conditioning is being applied at the transmitter output. If the signal is overequalized, this can present issues for the DS32EL0124 to achieve lock, and it may be possible that a more transition-dense pattern, such as a combination of K28.5 and Dxy.z words, is creating a scenario that the DS32EL0124 can remain locked.

Regards,

Michael

It looks like RS_B = High and DC_B = Low, so Remote Sense is disabled and DC-Balance is enabled. This allows the DS32EL0124 to be used with any transmitter, so long as the transmitter encodes data in the same way that the DS32EL0421 does and is AC coupled. From the schematic, I can see the AC coupling at the output of the AFBR transceiver, and the DS32EL0124 schematic looks correct.

Would you be able to get some more information about the transmitter and how the transmitter works, since they are not using the DS32EL0421?

The transmitter is an ALTERA Cyclone-V FPGA that is connected to an electrical-optical converter (AFBR57). When the FPGA starts up it sends first an endless stream of K28.5 Characters.

For example, it is important to keep the TXIN4 parallel input (Data Valid Input) to the transmitter high for 110 LVDS clock periods to allow the deserializer to lock properly. Also, it would be good for us to know whether any signal conditioning is being applied at the transmitter output. If the signal is overequalized, this can present issues for the DS32EL0124 to achieve lock, and it may be possible that a more transition-dense pattern, such as a combination of K28.5 and Dxy.z words, is creating a scenario that the DS32EL0124 can remain locked.

As mentioned in my first mail an in the description above the Serializer is starting to send K28.5 characters only . In my case 110 LVDS clock periods equal about 360 nsec. Right ? So every K28.5 sequence that is longer than 360nsec should be Ok.

Lets assume the serializer is active sending K28.5

Lets assume that the deserializer-board (DS32EL0124) was powered down and is now powered on

Now I have to set the cross-switch to a defined value and from that moment on the K28.5 stream is input to the DS32EL0124

Then for at least some seconds nothing more happens to the system.

When I decide to start data transmission I use a self written tool to activate data. That means that the Serializer is now sending 12 K-characters followed by 20 D-characters

followed again by 12 K-characters and so on.

So the condition you require with 110 LVDS clocks should be fulfilled.

I add the answers from my customer in green.

Best regards

Egon

Hello Michael,

attached the answer from my customer:

I changed the pull-down to a pull-up at pin DC_Bn. So I now have the configuration: RSn=1 and DC_Bn=1 on power-up.

In the first try I didn’t change any registers so the Descrambler and the NRZI ist still on all the time -> CDR ist not locking (LED ist blinking)

And the signal at the LVDS output looks strange because DC-Balance decoding is missing.

In the second try I also changed two register settings:

R[0x22] = 0x65 = Overwrite NRZ, Descrambler, Decode Bypass and Device Config

R[0x21] = 0x02 = NRZ off, Descrambler off, Do not bypass DC Balance, Remote Sense disable, DC Balance enable

I still get the unlocked CDR. But when I use my special procedure by switching from K28.5 to Dx.y I get a lock.

But there‘ s one drawback: The DC-Balance decoder is not working correctly because I get no data-valid on RxOUT4.

Instead I see something that looks like a fifth Bit.

 Best regards

Egon