DS90CR285: SAMPLING PROBLEMS

Hi Igal,

Please see my responses below to your questions.

Regards,
Ryan

1. I didn't connect the unused pins to GND according to datasheet, what can happen at this condition? can a switcing noise trnsfer to other bits and change the logic state?
[RH] Unused inputs (TxIN) are recommended to be tied to ground to avoid adding noise to your system. Can you share a schematic/layout of the design?

2. I didn't supplies the PLL voltage with isolated voltage, the PLL voltage connected with all the component voltage include FPGA, can it cause any sampling errors?
[RH] Sharing the PLL supply with other components can also be a source of noise and errors. Are you able to use ground and power planes, or is this not possible since you are sharing power with the FPGA. Can you confirm that you added the recommended bypass capacitors as well?

3. There is any new replacement component with more sampling window and low noise and jitter performance?
[RH] Are you using a DS90CR286 as a receiver in this application? Rather than recommend a new component, do you have the option to re-layout the board per the recommendations from the datasheet including how to connect unused inputs and isolating the supplies away from other noise sources such as digital and clocking components. To make your design more immune to noise, there is a board layout section of the datasheet. Did you follow these guidelines?

4. Can SN65LVDS93A replace this component?
[RH] This device is similar to the DS90CR285. My concern is that if you have noise issues on the DS90CR285 board, these will not be addressed by using the SN65LVDS93A.

thanks,
Igal Talor

Thanks Ryan,
I will check this issue more and I will be in touch about it.
Igal