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DS32EL0421: interface between "Sub-LVDS" and DS32EL0421

Part Number: DS32EL0421
Other Parts Discussed in Thread: DS32EL0124

Hi,

I would like to ask you a question about an interface between "Sub-LVDS" and this device.

My customer is planning to connect FPGA out which is "Sub-LVDS" with DS32EL0421.

Is it possible to connect "Sub-LVDS" with DS32EL0421 dilectly?

The main issues to connect seem to be needed to consider are as follows.

 I1) Sub-LVDS output is +/-75mV but DS32EL0421 is +/-100mV

 I2) Sub-LVDS needs +/-1% accuracy for external terminal resister, but DS32EL0421 has +/-15% internal resister.

The detail specification of Sub-LVDS is as below.

LVDS OUTPUT Spec
Item simbol Min TYP Max  
Outpu common voltage VCM 0.76 0.9 1.05 V
Outpu amplitude Vco 95 150 200 mV
Termination Zdiff 98 100 102 Ω
variation of VCM ΔVCM -25 - 25 mV
variation of Vco Δvco -25 - 25 mV
Clock duty TH/TL 45 50 55 %

LVDS AC Spec
Item simbol Min TYP Max  
Internal clock   - - 594 MHz
Set up time Tlvdssh 420 - - ps
Hold time Tlvdshd 420 - - ps

(LVDS out clock = 297MHz)

About I1), If it is not possible to connect directly, could you advise me how to realize to connect?

                Or could you tell me another apropriate device to connect?

About I2), Could you tell me the way to use external terminal resister instead of internal one?

                Or is it possible to provide me +/-1% device?

Thank you very much for your support in advance.

Best Regards,

  • Hi Suzuki-san,

    Can you confirm the “Sub-LVDS output is +/-75mV” statement?
    Typically the sub LVDS output is +/- 150mV (eg. SN65LVDS307, Differential output voltage magnitude)

    A sub-LVDS output can directly drive an LVDS input on the EL0421 device if the FPGA meet the EL0421 spec.

    Regards,
    Dennis
  • Hi Dennis-san,

    Thank you for your reply!

    I have confirmed the specification again.

    The output specification of the customer's is as below. (Yellow line)

    On the other hand, the specification of SN65LVDS307 is as below.

    I suppose that both specification of Sub-LVDS seems to be same...

    The "150mV" output means +/-75mV(based on common voltage), I guess.

    So, I think that DS32EL0421 can not receive "Sub-LVDS" output.

    And let me ask you again following questions, please?

     - Is it possible to provide the device which has internal +/-1% terminal resister?

     - Will you tell me the device to receive Sub-LVDS signal or "level converter" device if you know?

    Thank you for your great support.

    Best Regards,

  • Hi Suzuki-san,

    You don't need a device between your FPGA and EL0421. I suggest you to find out how the FPGA defines the Differential output voltage magnitude. An output waveform will help, as Sub-LVDS is an industry standard.

    The small difference in termination resistance will not make any difference.

    Regards,
    Dennis
  • Hi Dennis-san,

    Thank you for your reply!

    I understood.

    Regards,

  • Hi Dennis-san,
    I confirmed the application of my cutomer again.
    I mistook to understand the application, their application is "CMOS sensor camera" and CMOS sensor's output is "Sub-LVDS".
    That is to say, the cutomer plans to connect CMOS sonsor with DS32EL0421 directly.
    Have you ever experienced this kind of application?
    Do you have any idea to connect directly?
    Regards,
  • Hi Suzuki-san,

    Can you send the CMOS sensor camera datasheet to us? I don't think it is going to be an issue but would like to review the datasheet to confirm.

    Regards,
    Dennis
  • Dennis-san,

    I see.
    In fact, I could not get the datasheet from the customer but I will try to ask again.
    Regards,
  • Hi,we use ds32el0421 and ds32el0124 to transmitter image sensor data. We already get right clock from image sensor. But we can't get correct data ,those data is kept 0 forever!!! The lock signal of ds32el0421 is correct, keeping high. We try to modify "RS" and "DC_B" to "11,00,10,01",the results is dissappointed.
    thank you telling me why.