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DS90UB953-Q1: DS90UB953 MIPI input routing requiremnts

Sam Litvin
Prodigy 100 points
Part Number: DS90UB953-Q1

I see that the DS90UB953 MIPI inputs support polarity inversion, which is great.  However, I don't see anything regarding lane order reversal or lane swapping.  Is that possible?

Also, in the CSI-2 routing guidelines section of the datasheet on page 63, it says "Match trace lengths between pairs to be < 25 mils".  This is tighter than the MIPI spec for lane-to-lane skew.  Can you please explain the actual requirement?  Can the DS90UB953 tolerate more lane-to-lane skew and also lane-to-clock skew than the guideline suggests?

  • 0
    TI__Intellectual 2930 points

    Hello Sam

           DS90UB953 does not support lane swap or lane order reversal . DS90UB953 is fully MIPI-compliant. We do give a guidance of 25 mils but we can look at specific skew numbers (in ps) between lane-lane and lane-clock on a case-by-case basis and can provide more specific guidelines. Please provide the following:

    1. CSI-2 speed?

    2.clk-lane skew? (in pS)

    3.lane-lane skew? (in pS)

    Regards

    Vijay

  • 0 in reply to Vijaya Ceekala
    Prodigy 100 points

    Hi Vijaya,

          We want to be able to run the MIPI data lanes at up to 800 Mb/s.

          What I'm asking for is the maximum allowed skew.  At the moment, my data lanes range between 22pS and 44pS of delay, and the clock lane is at 12pS.

          I understand if that's too much, but I would like to understand what the actual requirement is.

    Thanks,

    Sam

  • 0 in reply to Sam Litvin
    TI__Intellectual 2930 points
    Maximum allowed skew per DPHY spec. on the traces is 1UI/50. At 800Mbps, this comes to 24ps. Based on the numbers you provided, there seems to be about (44 - 12 = 32ps skew between traces) . I believe that this will not meet the MIPI DPHY guidelines

    Regards
    Vijay