Hi,
I have a requirement wherein I have one single-ended signal that is to be split into 100 LVDS signals.
So I have given this single ended signal to SN74LVTH16245ADGGR single ended buffer.
At the input of this buffer, there is an LVDS receiver SN65LVDS390D. This single-ended signal is connected to 6pins of the single ended buffer SN74LVTH16245ADGGR
At the single ended buffer output, the signals are driven from 6 outputs and connected to 16pins of the one LVDS driver SN65LVDS387DGG.
With this system present, I'm not sure whether this splitting of signals will workout.
Can you please help me. Is there anything wrong with this implementation? Do I need to modify anything in this?
Below is the simple diagram for understanding.
Please help ASAP.
Thanks & Regards,
Nanjuda M