• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Subscribers 32 subscribers
  • Views 778 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DS92LV2412: LOCK status lost

ACGUY
Guru 11170 points
Part Number: DS92LV2412

Hello E2E,

They adopted DS92LV2412 for new product for scanner.
It communication failed in test before pre-mass production.
It occurs with a specific video(data) pattern.
LOCK status pin to been low at the specific data pattern.

Questions;
  -  Do you know the same case and what's cause?
  -  What are C0 and C1 in datasheet?

Regards,
ACGUY

  • 0
    TI__Mastermind 35130 points
    Hi ACGUY,

    C1 and C0 represent the embedded clock in the serial stream. C1 is always HIGH and C0 is always LOW.

    I found a similar case here: e2e.ti.com/.../791688
    where the issue was proper power filtering and layout.

    Regards,
    I.K.
  • 0 in reply to Ikechukwu Anyiam
    Guru 11170 points
    Hello I.K,

    Thank you for your advice.
    >> where the issue was proper power filtering and layout.
    Yes. I suggested the your advice to customer. There are LC-filter on 1.8-V power supply for PLL. They changed cap from 0.1-uF to more than 0.22-uF. The issue was cleared. However, there is no theoretical basis about it. It is prescribed to 50-mVpp in the dataheet. Before change the cap, noise of PLL-Vcc was 37-mVpp. LOCK-out happen at parallel clock less than 10-MHz. When more than 10-MHz, it is normal.

    Why LOCK-out is happen?
    Does lock-out occur when the clock frequency decreases?

    Regards,
    ACGUY
  • 0 in reply to Ikechukwu Anyiam
    Guru 11170 points
    Hello I.K,

    I have update.

    1-
    The issue happened on around 9-MHz parallel clock only, not happened on less than 9-MHz or over than 10-MHz.

    2-
    Clock Jitter for input to Ser side is normally. It's less than 0.5-UI.

    3-
    We strengthened for LC-filter caps of each 1.8-V power, only the PLL power supply had the effect.


    DS92LV242x using more than 10-MHz clock.
    I think that DS92LV241x has bug for around 9-MHz parallel clock.
    Do you have Noise Resistance data about DS92LV241x for 9-MHz parallel clock?


    Regards,
    ACGUY
  • 0 in reply to ACGUY
    TI__Mastermind 35130 points
    Hello ACGUY,

    I will check if we have any such data. For clarification, I have a few questions:

    1) Has the issue been fixed now that they added the capacitor?

    2) Before they added the capacitor, did they see the issue on multiple units? Were there any units that did not have the issue?

    3) If there were units that did not show the issue, were they able to swap it with a bad unit and reproduce the issue?

    Regards,
    I.K.
  • 0 in reply to Ikechukwu Anyiam
    Guru 11170 points
    Thank you for your response.

    1)Yes. P-CLK is 9-MHz, changed the cap from 0.1-uF to 1-uF/6.3V/1005/X7R .
    This cap's Z is be lowest at around 9MHz.

    2)Yes. there are 50-units. There are 5-units have issue.

    3)Yes. The problem is accompanied.



    If you know ,,,
    In the datasheet p10,
    (1)
    Supply noise testing was done with minimum capacitors on the PCB.
    A sinusoidal signal is AC coupled to the VDDn (1.8V) supply with amplitude = 100 mVp-p measured at the device VDDn Pins.
    Bit error rate testing of input to the Ser and output of the Des with 10 meter cable shows no error when the noise frequency on the Ser is less than 750 kHz.
    The Des on the other hand shows no error when the noise frequency is less than 400 kHz.

    I think, this sentence mean is "The noise frequency shall not exceed 400 kHz.".
    Is it correct?

    Regards,
    ACGUY
  • 0 in reply to ACGUY
    TI__Mastermind 35130 points
    Hi ACGUY,

    I believe this was handled over email. Below is the answer given:

    There are no concerns about 9MHz particularly. For the supply noise, normally we would prefer to have it below 20mV typically. With a 10uF cap and ferrite beads, normally the noise is way below this figure. This device was tested with the LV24EVK, and most of the power rails have a 22uF, 0.1uF, and a 0.01uF cap because if this unlock issue was seen it 100% would have been addressed right away. We have been using 20mV for our high speed devices, and have tried to recreate 20mV noise with normal supply coupling caps but it is very difficult because supply coupling caps act like a low impedance to ground. Also, LDO switching frequency should be above loop bandwidth of the data rate. This way, the device loop filter can attenuate this noise.

    In summary, adding a lot of supply caps , ferrite beads, and a correct choice of LDO can take care of this issue.

    Regards,
    I.K.