ESD protection inherent to TPL7407L

Cedrick,

Which pin(s) are being damaged?
Inputs, outputs or COM pin?

Hello Ron,

For now we have seen only input pins being damaged. However, we want to protect both inputs and outputs since they are subject to ESD.

Cedrick,

The devices was ESD tested with HBM values 500V to 4,000V with no failures. CDM from 250V to 1500V with no failures.
Inputs and COM pin have NMOS based ESD cells and outputs are self protecting due to their massive size.

I have asked design if any ESD impulse was tested. This may take a couple weeks unless business case warrants expediting.

For inputs a R-C-R filer should be very helpful (resistors in series, capacitor terminated to ground).

Ron,

We have been testing a couple of ESD suppressors and TVS, but each time the the IC would fail because of the overshoot voltage (~300V) caused by the initial discharge. Could you recommend a protection device that would be efficient enough to protect the driver, or else typical values for the R-C filter you suggest?

Thanks,

Cedrick

Cedrick,

Do you know the width of 300V pulse?
What is the normal VIL, VIH, and input frequency?
The input impedance of the TPL7407 is very high (1 Mohm) so a lot of isolation can be implemented.

Hi Ron,

The pulse width would be ~50ns. Standard operation voltage 0-24V. Max rise/fall time: 200ns. 60kHz max operating frequency.

We have observed damage on the outputs as well, always after negative discharges.

Cedrick

Cedrik,

Are the input and outputs connected to cables and this is why IEC 4kV is being tested?

I have worked on an input filter to limit 300V 50nS and pass 60kHz 0V to 24V well. R1, R2, R3, C1

Protecting the outputs will be more difficult.

Do you know how ULN2003A  preforms in the normal application and IEC testing?

Hi Ron,

Yes, the drivers (output and input pins) are connected to cables. We originally used ULN2003A but switched to TPL7407L before performing IEC testings because the latter has better VoL and performance overall respectfully to our application.

The suggested filter needs 4 components per input. Unfortunately, we do not have enough board space to implement this solution. We think adding a ferrite bead and a ultra low Rdyn ESD suppressor can work as well for the input as the outputs (ferrite on outputs only), which bring us back to the former question: can you provide dynamic resistance of the TPL7407L input and output pins to help us select the best protection device?

Thank you,

Regards,

Cedrick

Cedrick,

ESD experts have been contacted and they have started working on the requested data.

Cedrick,

Attached are the input pin TLP characteristics.

TPL7407 IN ESD.zip

Hi Ron,

Thanks for the screenshots. That will surely help us design an efficient protection. Please let us know when you get the results for the outputs.

Regards,

Cedrick

Cedrick,

After much searching we did not fin TPL data for outputs.
I will need to request that new data be taken.

Hi Ron,

any update on this?


Many thanks,

Cedrick

Cedrick,

No updates. Because the output self protects there is no standard cell that already has data recorded.
It will take significant effort to get this priority.
Do you have a business case information to share?

Ron,

We have noticed that the outputs are particularly subject to ESD damage when the FETs are turned on (in our case, sinking to GND). We will go forward with a protection including a TVS and a ferrite bead in series with the output. Our application operating at a quite low frequency, the ferrite will not affect performances.

Regards,
Cedrick