TUSB1310A: External Clock and Power Supply Filtering

Hello John,
Please see the answers below. Most of the requested information is not available. Sorry for that.

1. For TUSB1310A external clock: which input is recommended for the best Tx and Rx jitter performance:
a. XI (A12) as single-ended 1.8V clock input ?
b. REFCLKP/REFCLKN (C13/C14) as differential clock input ? These pins are marked reserved in TUSB1310A datasheet but shown in the SuperPHY and Ultrahub schematics for old TUSB1310.

Answer. REFCLK is no longer used as REFCLK, please use XI instead.
2. We are revising the TUSB1310A power supply filtering and decoupling to bullet-proof the Tx and Rx jitter performance and would like to know some more info on certain pins. Please confirm/answer the following ?

a. Pin P12 VDDA3P3 appears to be ONLY used for USB2, is this correct ? If so we will not focus on its filtering/decoupling.

Answer. I do not have that information and the datasheet do not state that. I recommend install decouple caps.

b. Pin C10 VDDA1P8 in the Ultrahub schematic is named US3_VDDO_1P8 and has optional connection to digital 1.8V. What I/O does this pin provide power to and are we better off leaving it separated from sensitive 1.8V analog power ?

Answer. I do not have that information. I recommend keep separate VDDA1P8 and VVDO1P8.

c. Pin C11 VDDA1P1 in the Ultrahub schematic is US3_VDDO_1P1. Which I/O does this pin provide power to and are we better off leaving it separated from sensitive 1.1V analog power ?
Answer. I do not have that information. I recommend keep separate VDDA1P1 and VVDO1P1.


3. TUSB1310A Pin C12 “VDDA1P1” in the Ultrahub and Superphy schematics is the SuperSpeed PLL power pin “VDDA1P1SSPLL”. In order to guarantee USB3 Tx and Rx jitter compliance as host and as device (as device is a main use-case which is the more difficult of the two) with good margin, I would like to consider adding an RC filter to PLL pin. Questions are:

a. Is the pin C12 PLL pin a constant (DC) current load (i.e. di/dt is zero)? If so, then an RC filter is a good filter topology for this pin.
Answer. I do not have that information. I recommend follow the schematic of the reference design.

b. What is the typ and max current (mA) for this pin ?

Answer. The power numbers regarding the VDDA1P1 pins are located at Device Power Consumption section of the datasheet. Unfortunately those are for the all rail instead of a specific pin.

c. I am considering a typical PLL RC filter such as R of 0.43 ohm or 0.56 ohm and C of 1uF, 2.2uF, or 4.7 uF, depending on current (mA) of pin and corner frequency required. With RC of 0.43 Ohm and 2.2 uF (2.0 uF with 1.1V DC bias), this results in corner frequency of 185KHz for example. Is the jitter transfer function of Pin C12 to Tx jitter and Rx tolerance available?
Answer. The jitter tolerance isn’t available .

Regards,
Gerardo