Other Parts Discussed in Thread: LSF0204
Hi,
How should the TXB0108 respond on input pulses shorter than tW_min (=10ns for the 3.3V<->5V case) - in order of, say, 1-3ns?
Let's consider the following scenario:
The TXB0108 is used for voltage level translation between 5V CPU and 3.3V static RAM data bus.
During a read transaction the CPU releases the data bus and then asserts the OE (Output Enable) signal.
Upon OE assertion the RAM starts driving the data bus.
There is a short interval - say, 1 to 5 ns according to the RAM specification - before these output data become valid.
It means that data lines may change their state one or more times during that time.
How will the edge-rate accelerator within the TXB0108 react on these short pulses?
BR,
Denis