Output state of D-flip flop

Keerthika Subramanian

Other Parts Discussed in Thread: SN74LVC1G374

I am using the TI device SN74LVC1G374. Regarding it, I have a doubt about its output state during power up. In this configuration for the D-Flip flop, the clock signal is given by Shut down_TTL. It is held at logic low after powerup till needed and no clock signal is given during powerup. The output state before powerdown is logic low. What will be the output state in this configuration? Thanks in advance.

over 10 years ago

0 Chris Cockrill over 10 years ago

TI__Mastermind 46480 points

The output state on all flip flops will not be guarranteed until after the first valid clock signal or they can be controleed by a reset or clear pin.

0 Keerthika Subramanian over 10 years ago in reply to Chris Cockrill

Prodigy 20 points

Then corresponding to the above circuit can i expect a voltage of 5V at the open pin attached to Q?

Secondly can the unpredicted state before the first clock reach a voltage level of 0V?

0 Chris Cockrill over 10 years ago in reply to Keerthika Subramanian

TI__Mastermind 46480 points

The output will power up driving when OE is tied low and it can drive high or low.

You might consider using the SN74LVC1G74 and use the pre or clr pin to set the output.

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Output state of D-flip flop