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Daisy Chaining SN74HC595

Alan Howard
Prodigy 85 points
Other Parts Discussed in Thread: SN74HC595, SN74HC244

Service Request# 1-1875307123

Problem:
SN74HC595 connecting QH' to SER to daisy chain parts. Random shift errors. It appears in the timing diagram that QH' appears to change on rising edge of SRCLK. On the next IC where SER is fed by the previous QH' is changing as the clock is changing creating a race condition. 
 
Steps Needed to Recreate Problem:

I have 16 SN74HC595 daisy chained to control 128 outputs. Only one out put is on at a time. 
If I cycle through the outputs over and over, randomly the active output is one or two positions off.


 

  • 0
    TI__Guru* 96681 points
    Alan,

    Can you post a full schematic and scope shots of the errors?
  • 0 in reply to Emrys Maier
    Prodigy 85 points

    Here is a partial Schematic. I don't have a scope capture of the error. Happens too randomly to capture on a scope. Looking at the waveforms when it functions correctly though, the QH' transitions at the same time as the CLK.

  • 0 in reply to Alan Howard
    TI__Guru* 96681 points
    Can you give me a scope shot or timing diagram of TSTSTB and TSTCLK? Also, can you tell me about what this is doing exactly? I haven't seen a setup with this many 595's chained before!
  • 0 in reply to Alan Howard
    TI__Guru* 96681 points

    Sorry to keep asking questions without giving anything back. Let me tell you what I'm thinking.

    It's possible that by separating out RCLK and SRCLK a bit you can eliminate any race conditions. I'm just wondering how all the timing works in your circuit to see if this is possibly a solution.


    I see now that SRCLK and RCLK are completely separate and you should be able to use SRCLK only to push data through all of your shift registers.  Adding a delay to the clock between stages should eliminate this issue.  An HC buffer (SN74HC244, octal buffer)  would add ~11ns of delay per buffer.  By running the clock into the first buffer and chaining the rest end to end, you could create 8 slightly delayed clock signals.  To be certain I would use 2 and put a delay between every HC595, but it would probably work fine with a delay between every 2.

  • 0 in reply to Emrys Maier
    Prodigy 85 points

    SRCLK over RCLK

    SRCLK over RCLK zoomed on RCLK

    SRCLK over QH’ of the third 595 in the chain. I was able to capture this at the time of a problem.

    In your solution to delay the SRCLK going to each of the 595s in the chain, is the goal to clock the QH' signal from the previous 595 into the SER of the 595 at the beginning of SER going low or at the end?

     

     

  • 0 in reply to Alan Howard
    TI__Guru* 96681 points
    The goal would be to have the last device in the series shift its contents first. For example, if you had two devices with this data to shift: 12 34. You could shift the second one first and get 12 23, then shift the first to get: 01 23. If the first one shifts before the second, the results would be 01 13, which is obviously an error. I know this is an odd example, but does it make sense?
  • 0 in reply to Emrys Maier
    Prodigy 85 points

    I am not following your data. what t do the numbers represent?

    Here is my clocking process reduced to two devices. I want to set the QE of the second device low and the rest of the Q signals high. I set device 1 SER low and clock SRCLK once, then set SER high and clock SRCLK 3 times (device 1 register QD is low, this is so that when I clock out to the desired position all of the out puts after it are high, the low goes past the end). Then I set SER low and clock SRCLK once, the set SER high and clock SRCLK 12 times to move the low to the device 2 QE register position, then I toggle RCLK to update the outputs.

    So I understand using the buffers to delay the clock. Are you saying that the first device in the chain would get the most delayed clock?

  • 0 in reply to Alan Howard
    TI__Guru 57480 points
    Hi Alan ,

    I understand the suggestion from Emrys is to have some propagation delay of the buffer to offset the arrival of the clock signals to the later part of the Daisy chain while the valid output from previous device is fed into the input of the HC595 .The speculation is the adjustment of hold time (valid data before clock) can be satisfied with the addition of buffer while also improving signal integrity of clock.
  • 0 in reply to ShreyasRao
    Prodigy 85 points
    This seems like it is it is still very close to a race condition of the SRCLK going high while the QH' is going low. I just thought of another possible idea. If RCLK was the inverse of SRCLK and I used QH instead of QH' to feed SER of the next IC? This way QH goes low half a clock cycle before SRCLK goes high and goes back high half a clock cycle after, removing the race condition. Does this sound like it would work?
  • 0 in reply to Alan Howard
    Prodigy 85 points

    The first waveform is SRCLK to all 595s

    The second waveform is RCLK to all 595s. This is the idea of creating it as an inverse of SRCLK is shown.

    The third line is SER of the first 595

    The fourth line is QH of the first 595 which is connected to SER of the second 595. This uses the RCLK idea.

    The fifth line is QH of the second 595 which connected to SER of the third 595. This uses the RCLK idea.

    The sixth line is QH' of the first 595 which was connected to SER of the second 595. This is the current design.

    The seventh line is QH' of the second 595 which was connected to SER of the third 595. This is the current design.

    The current design appears to have a race condition between QH' and SRCLK. The current design has intermittent issues when used with a series of 16 595s to create a 128 bit shift register. Do you think the RCLK idea will resolve this?

  • 0 in reply to Alan Howard
    TI__Guru* 96681 points
    RCLK should not affect the shifting of data -- the best fix in my opinion is still to add delay to the clock so you have a definite shift time for each part.