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SN74AUC1G79: Problem on the Output Q pin

user4760726
Intellectual 1185 points
Part Number: SN74AUC1G79

Hi team,

One of our customers is facing a problem related to the behavior of OUPUT Q. The customer has the circuit like the schematic below. They found out that when the IC is powered on, the OUTPUT Q would go high level befroe D pin goes to High level. Please refer to the wavefore below. However, if a probe is placing on the CLK path, the behavior of OUTPUT Q does no have this kind of behavior. Do you know what is causing this problem? Or does the customer need to add another circuirty to prevent it? Thanks for your support and time. 

Leroy Song

  • 0
    TI__Intellectual 2050 points
    Hi,

    This seems like the SN74AUC1G79 is in some sort of an unknown state upon start up, since upon immediate start up it goes HIGH.

    Probes have a small amount of capcitance, so you are loading the CLK slightly when probing it. I find it odd that this would cause the problem to no longer occur.

    Has your customer tried this with another SN74AUC1G79 to see if the problem is replicable?

    Where is the TXE_Data and CLK coming from?

    A pull-down resistor on the D input might help start the device in a known state (LOW) upon start up.

    Regards,
    Joe
  • 0
    TI__Intellectual 2050 points

    I want to follow up on this post. Please be aware that the device has an unknown output on start-up. In order to have a known output, a valid input must be clocked to the device.

    -Joe