Original question:
Hi All，
We found some TI SN74HCT273 needed Din hold time(th) is more than 600ns, if the Din level be switched in less than 600ns after clk rising edge, we can see switched Din status be latched.
Datasheet only defined minimum value which is 0ns. Could you please check the distribution of Din hold time? How long time we need hold the Din signal after clk rising edge to make sure it can be latched?
Hi Dylan,
Here is our schematic diagram, there are 2 SN74HCT273s, each SN74HCT273 contains 8 D-flip flops, total 16 D-flip flops be connected in serial. The 9th D-flip flop is the 1st D-flip flop of the 2nd SN74HCT273(U2).
We put a high level on Din of the first D-flip flop(U1 1D) after clear signal, expect the high level will be transfer to next stage after each rising of clock signal. The 16th D-flip flop output(U2 8Q) will get the high level signal after the 16th clock rising edge. Most of circuit are working as we expected. But some of board is not working as we expected, the 16th F-flip flop output will be high level after 15 only clock rising edge. We found it’s the D-flip flop 9 captured high level at the 8th clock rising edge.
This chart is from a functional board, CH1 is clock signal, CH2 is the Din of the 9th D-flip flop, CH3 is the output of the 9th D-flip flop. The 8th clock rising edge make the 8th D-flip flop ouput turned to high level and the 9th clock rising edge make the 9th D-flip flop ouptput turned to high level. This is expected.
Next chart is from a defect board. CH1 is clocl signal, CH2 is the Din of the 9th D-flip flop, CH3 is still the output of the 9th D-flip flop. We found the 8th clock rising edge make both the 8th D-flip flop and the 9th D-flip flop output turned to high level.
We zoom in on time domain, on the functional board, we get chart as blow. CH2 is clock signal, CH1 is input the 9th D-flip flop, the rising edge of clock is the 8th rising edge after reset. The 8th D-flip flop outut turned to high level 700ns after clock rising edge.
On defect board, we get this chart. The 8th D-flip flop output turned to high level 610ns after the 8th clock rising edge. Then the high level be captured by the 9th D-flip flop on the 8th clock signal rising edge.
It seems the 9th flip flop input signal don’t have enough hold on time on the 8th clock rising edge, make the high level be captured by 9th flip flop in the 8th clock rising edge, it was expected to capture a low level signal on the 8th clock rising edge.
We need to understand how much hold on time the chip need to make sure no unexpected trigger.
Please let me know if you still have queries before answer out questios!
Thanks.
Hi Dylan,
1. I assume that U2 flip flop outputs are connected to the inputs like U1 correct?
Yes, each U2 flip flop output be connected to next flip flop input like U2
2. It seems like you have boards that are working and some that aren't. Have you swapped the device that is not working with one of the ones that is working? This could be beneficial. If the new device fixes the problem there could be an issue with the device.
if we swap 2 devices, the circuit will work, but we cannot preselect device and mount them on different location. And this is a batch failure case, not an occasional case. This case is more happened when U1 and U2 are from different datacode, if we put one particular datecode component on U1 position, the other particular datecode on U2 postion, then the board will not work. Again, swap them, the board will work. We did not see this failure if U1/U2 were from same datecode so far
We think this problem is caused by difference batch components have different ”th” request, the specific of “th” on datasheet only marked MIN value, we don’t know the distribution of “th” among different batches. Can we know what’s the typical and MAX value of “th”?
