TINA/Spice/SN74AVC16T245: Output duty issue of SN74AVC16T245 spice models

Xiaobin,

I am sorry, this is an old Hspice model and somehow we cannot locate the unencrypted file, thus we cannot verify further the cause of the shifted duty cycle that comes out of the Hspice model. The duty cycle is also strongly dependent on the frequency of operation in the actual IC. With 50% input DC at low frequency, the output DC is ~50%. For higher speed of operation > 300Mbps, the DC distortion could start to drift from 50% towards 45% - 55%. What is the frequency of operation?

Would you consider the SN74AXC8T245 device and its IBIS model for simulation and usage which should be much better than the IBIS model of SN74AVC16T245.

Xiaobin,

The datasheet in the features section mentions the max data rates supported by the device.
1.2V is 100Mbps, 1.8V is 200Mbps given the ideal load capacitance. You are operating at 300Mbps@1.8V and 1.2V which cannot be guaranteed.
Hence, the duty cycle distortion is seen now.
The AXC behaviour will be similiar to AVC.

Hi Xiaobin,

The AXC is a new family of devices equivalent (P2P) with the AVC devices, but operates up to 0.65V.

So, instead of the SN74AVC16T245, you could consider using the SN74AXC8T245 *2 in the RJW package which will be smaller than the AVC16T.

The weak 1.8V simulation is a corner case, and as I had mentioned these numbers in the datasheet features section are max data rate in typical conditions.

A typical physical IC should have better (lower) duty cycle distortion performance.

Xiaobin,

We do not have a data book for AXC. but you can find all products here below:
www.ti.com/.../products.html
and read about the application note on glitch free power sequencing here:
www.ti.com/.../scea058a.pdf

The data rate performance for 1.2 and 1.8V is similiar as the AVC.