Part Number: SN74AUP1G74
Hello, I intend to make a modified WDT circuit using SN74AUP1G74 to maintain WDT output signal low after WDT timeout event.
Most WDT dedicated circuits implement pulsating output after WDT event, but in my application I need a logic signal steady in 0V (0V on WDT_SIG will keep running a FAN until human intervention).
So, at start, we need a logic 1 on SN74AUP1G74 output (thus the /PRE pin tied to GND), and only after WDT timeout, the WDT pulses will trigger the flipflop's clock to output the desired 0V output
My concern is that during power up, the rising signal on CLK might be considered as a clock transition, and data latched to output. I understand that this component has a preset pin specifically for this scenario, but I could not find any specific timing information for this case: how long until valid VCC on flip flop will it take to a variation of CLK pin is considered a "valid edge transition"
I see I have misinterpreted the usage of /PRE signal.
I have modified the circuit adding an RC filter on this pin (RC=~290 ms). I believe this is enough time to stabilize the VCC and /WDO signal from STWD100, forcing Q to remain HIGH during the ramp up of /WDO-CLK signal.
I know it is not advisable to put RC on a MOSFET input (as discussed before, and according to datasheet), but at the time the voltage reaches the undefined input state, the CLK and D signals will already be in stable states, thus not changing the output.
Still not sure if this will work. Any D type flip flop like this with HIGH to LOW clock edge latching? I think this could solve the problem as well without the need of the RC filter on /PRE.
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In reply to Arthur Silveira:
Whatever happens on CLK does not matter for initialization, because the initial state is unknown to begin with. You always need a low pulse on PRE.
During power up, there is no initialization time; after the supply has reached the minimum allowed voltage, the state at the inputs is reflected on the outputs after at most tpd has elapsed.
If you don't like the behaviour of the CLK input, don't use it. Just connect WDO to CLR.
Alternatively, create an S/R latch from two NAND gates (SN74HCS00 or SN74LVC2G132 or 2× SN74AUP1G98 have Schmitt-trigger inputs).
In reply to Clemens Ladisch:
Thank you so much for your answer. I really wanted to create a small solution due to board space limitation.
You said that during power up, the state of the input is reflected on the output. At first I thought about connecting D to VCC would solve the problem (since D voltage would always be equal to VCC, hence high state), but still hard to predict the behavior of /PRE and /CLR voltages.
But then I really like your idea of using /WDO tied to /CLR instead of CLK.
To solve the initialization problem, I then thought about using the same WDT reset pulse into CLK. This way, while the circuit is operating normally (WDT_rst pulses coming from MCU) a logic 1 will keep being latched to Q output. if MCU stops working, no more pulses on WDT will generate a pulse on /PRE, producing the desired 0V on the output. So initial unknown state is not a problem, since once the circuit starts running, it will go into desired state (loginc 1 on output), and if it even starts with MCU locked, after WDO timeout, low pulses on /CLR will clear the output anyways
(see circuit below)
In this case, do you think I still need a low pulse on /PRE to get this working? Do you see any other possible issue?
Thank you once again! Best regards,
I said "after", not "during". As long as there is no rising edge (or PRE or CLR) after power up, the output state is unknown.
This circuit looks OK. Very nice trick with the WDT_rst signal! If you do not care about the initial state, you indeed do not need a PRE pulse.
There is an application note Latching a Watchdog Timer, but it applies only to WDTs with a programmable reset delay.
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