Other Parts Discussed in Thread: CONTROLSUITE, C2000WARE
Hello All,
I have a sw state machine that is currently running within Timer1 interrupt:
interrupt void cpu_timer1_isr(void) { CpuTimer1.InterruptCount++; GpioDataRegs.GPASET.bit.GPIO9 = 1; GpioDataRegs.GPACLEAR.bit.GPIO9 = 1; cntOutputsHigh = 0; cntOutputsHigh += GpioDataRegs.GPADAT.bit.GPIO2; cntOutputsHigh += GpioDataRegs.GPADAT.bit.GPIO4; cntOutputsHigh += GpioDataRegs.GPADAT.bit.GPIO30; cntOutputsHigh += GpioDataRegs.GPADAT.bit.GPIO31; if(cntOutputsHigh != oldCntOutputsHigh) { oldCntOutputsHigh = cntOutputsHigh; switch(cntOutputsHigh){ case 0: GpioDataRegs.GPASET.bit.GPIO5 = 1; // Take 1x bit low (J1-3) GpioDataRegs.GPASET.bit.GPIO8 = 1; // Take 2x bit low (J1-12) GpioDataRegs.GPASET.bit.GPIO25 = 1; // Take 3x bit low (J1-6) GpioDataRegs.GPBSET.bit.GPIO39 = 1; // Take 4x bit low (J1-14) break; case 1: GpioDataRegs.GPACLEAR.bit.GPIO5 = 1; // Take 1x bit high (J1-3) GpioDataRegs.GPASET.bit.GPIO8 = 1; // Take 2x bit low (J1-12) GpioDataRegs.GPASET.bit.GPIO25 = 1; // Take 3x bit low (J1-6) GpioDataRegs.GPBSET.bit.GPIO39 = 1; // Take 4x bit low (J1-14) break; case 2: // GpioDataRegs.GPASET.bit.GPIO5 = 1; // Take 1x bit low (J1-3) GpioDataRegs.GPACLEAR.bit.GPIO8 = 1; // Take 2x bit high (J1-12) GpioDataRegs.GPASET.bit.GPIO25 = 1; // Take 3x bit low (J1-6) GpioDataRegs.GPBSET.bit.GPIO39 = 1; // Take 4x bit low (J1-14) break; case 3: // GpioDataRegs.GPASET.bit.GPIO5 = 1; // Take 1x bit low (J1-3) // GpioDataRegs.GPASET.bit.GPIO8 = 1; // Take 2x bit low (J1-12) GpioDataRegs.GPACLEAR.bit.GPIO25 = 1; // Take 3x bit high (J1-6) GpioDataRegs.GPBSET.bit.GPIO39 = 1; // Take 4x bit low (J1-14) break; case 4: // GpioDataRegs.GPASET.bit.GPIO5 = 1; // Take 1x bit low (J1-3) // GpioDataRegs.GPASET.bit.GPIO8 = 1; // Take 2x bit low (J1-12) // GpioDataRegs.GPASET.bit.GPIO25 = 1; // Take 3x bit low (J1-6) GpioDataRegs.GPBCLEAR.bit.GPIO39 = 1; // Take 4x bit high (J1-14) break; default: break; } } }
The logic is working fine, the problem is that the interrupt timing is inconsistent.
Here's the init code:
ConfigCpuTimer(&CpuTimer1, 86, 1); //
Using gpio9, I see the following using a data acquisition system:
So, there are about 12 set/clears in this 500us window, and they are disbursed randomly through time.
I suspect other interrupts are taking precedence over my state machine routine embedded in the timer1 isr. That would explain the varying period.
I see in the manual (SPRS698D) a reference that looks promising:
Should I reconfigure my timers to use timer0 as the interrupt source for my state machine?
Any other ideas or suggestions?
Thanks in advance for your valuable input!