Hercules EMIF documentation

Hello William,

I have forwarded your question to one of our experts and they should respond soon.

William,

The BA lines are multifunction.  If you are accessing SDRAM they act as the bank address.

If you access an async memory (different chip select line) then BA holds either an LSB or MSB of the asynchronous address.   Whether it's an LSB or an MSB depends on the width.   If the async is x8 then BA[1:0] will have address A[1:0].  But if the memory is x16 then you only get A[1] on BA[1] and A[0] becomes an MSB.

All these behaviors are documented in the EMIF TRM chapter.   That would be for example SPNU499B or a similar doc (we have several TRMs depending on which Hercules you are using, but the TRM is linked in the product folder on ti.com along w. the datasheet and errata for each part #.).

Thank you for the explanation.

I was not able to find any reference to an EMIF TRM on the RM3 product page:

http://www.ti.com/lsds/ti/microcontroller/safety_mcu/rm4_arm_cortex-r4/tech_docs.page

Could I suggest that the datasheet be modified to callout a reference to the EMIF TRM document?

But if the memory is x16 then you only get A[1] on BA[1] and A[0] becomes an MSB.

I am unable to comprehend the above. In the TRM, its mentioned for interfacing 16-bit memory to connect EMIF_BA[1] with A0 of  memory device. 

What is the above statement trying to say, please explain, (I am talking about page no 615 of SPNU503B).

Regards

Anila

Hi Anila,
Since you have created a new thread for the EMIF questions I will suggest that you continue on the new thread. This is a closed thread and sometimes questions asked on a closed threads may be missed out.

Okay, no problem, I got the answer in the new thread.

Regards
Anila