TMS570LC4357 and slow program execution

Hello Jiri,

  Is the cycle difference measured the first this test function is called? Can you call this function at least once and obtain the cycle difference based on the 2nd or the subsequent calls? I'm suspecting that these instructions are not yet filled in the cache the first time you call the function.

  In addtion, you can use the event counters to count certain types of events to better understand what is going on? For example, you will program the PMU event counter to count events such as instruction cache miss so we know if there are any cache misses executing these NOPs.  

I did some more measurement and it looks strange. It looks, that problem is NOT in instruction cache, but processor wait for instructions. Why?
I also made test to measure it 4 times in one (function speedTest2) and it mesure 4 times same value 81 cycles.

Here is PMU results in same order as in ARM DDI 0363E. All values are including measure overhead, see to measure code bellow.

Event #  result  note
0x01          0   Instruction cache miss.
0x03          0   Data cache miss.
0x04          0   Data cache access.
0x06          1   Data Read architecturally executed.
0x07          2   Data Write architecturally executed.
0x08         70   Instruction architecturally executed.
0x5e          1   Dual-issued pair of instructions architecturally executed.
0x09          0   Exception taken.
0x0A          0   Exception return architecturally executed.
0x0B          0   Change to Context ID executed.
0x0C          4   Software change of PC, except by an exception, architecturally executed.
0x0D          2   B immediate, BL immediate or BLX immediate instruction architecturally executed
0x0E          2   Procedure return architecturally executed, other than exception returns, for example, BX Rm; LDM PC.
0x0F          0   Unaligned access architecturally executed.
0x10          0   Branch mispredicted or not predicted.
0x11        238   Cycle count.
0x12          2   Branches or other change in program flow that could have been predicted by the branch prediction resources of the processor.
0x40        142   Stall because instruction buffer cannot deliver an instruction.
0x41          2   Stall because of a data dependency between instructions.
0x42          0   Data cache write-back.
0x43          1   External memory request.
0x44          0   Stall because of LSU being busy.
0x45          0   Store buffer was forced to drain completely.
0x46          0   The number of cycles FIQ interrupts are disabled.
0x47         19   The number of cycles IRQ interrupts are disabled.
0x48-0x5d     0
0x5f-0x7e     0
0x7f          238  ?       

And here is measure code:

        U32 event;
        pmuSetCountEvent(2, eventTest);
        event = pmuGetEventCount(2);
        speedTestResult = speedTest();
        eventResult1 = pmuGetEventCount(2) - event;

And here is complete asm code:

8407.speedTest.S

PS: all ASM functions are aligned to 64bit. If it is not aligned, code execution is slower (from 81 to 85 or 91 cycles). Is it impact of flash prefetch unit and 64 bit internal bus ?