RM4x Hercules Users,
There will be silicon revisions to the RM4x Hercules product line to fix several critical issues.
- RM48 Rev C -> Rev D
- RM46 Rev B -> Rev C
- RM42 Rev A -> Rev B
The Part Change Notification (PCN) will be sent the end of June, 2015. More detailed information on the change will be available at that time.
This post will provide the following information for RM4x products.
- Which errata will be fixed in which product family.
- Schedule summary
- Impact of the fix.
Which errata will be fixed
The errata that will be fixed are listed in the first column of the table below. There is a column for each RM4x device family. Meaning of “Fixed” is obvious. N/A means the errata does not apply to that device family. Errata that are listed in the errata sheet and not listed in this table will not be fixed.
|
Errata |
RM48 |
RM46 |
RM42 |
|
Power-on reset during bank 7 Sector erase may corrupt other sectors (erratum DEVICE#B041) |
N/A |
N/A |
Fixed |
|
Reads of Bank7 may be corrupted by short glitches on nPORST pin (erratum DEVICE#B042) |
N/A |
N/A |
Fixed |
|
Incorrect Write to External Memory using Store-Multiple CPU instruction (erratum DEVICE#B064) |
Fixed |
Fixed |
N/A |
|
CPU write to peripheral or EMIF may be lost (erratum DEVICE#B071) |
Fixed |
Fixed |
N/A |
|
PBIST ROM Algorithm Doesn’t Execute (erratum PBIST#4) |
Fixed |
Fixed |
Fixed |
|
Change to PLL Lock Time (erratum SWF021#44) |
Fixed |
Fixed |
Fixed |
Schedule Summary
The following table summarizes the schedule for the RM4x product family. Samples will be available as part of the PCN process. Superset configurations of the device family will be available first followed by all P/Ns.
|
Milestone |
RM48 |
RM46 |
RM42 |
|
Development Samples |
Now (TMS Rev C) |
Now (TMS Rev B) |
Now (TMS Rev A) |
|
TMS release |
Jun/15 (Rev D) |
Jun/15 (Rev C) |
Jun/15 (Rev B) |
|
Production Samples (<200units of superset P/Ns) |
Jun/15 (Rev D) SuperSet: RM48L952 |
Jun/15 (Rev C) SuperSet: RM46L852 |
Jun/15 (Rev B) SuperSet: RM42L432 |
|
Production Samples (All P/Ns) |
Sep/15 (Rev D) |
Sep/15 (Rev C) |
Sep/15 (Rev B) |
|
Production Volume Shipments |
Nov/15 (Rev D) |
Nov/2015 (Rev C) |
Nov/15 (Rev B) |
The status of the safety certifications of the current revisions of the RMxx production qualified devices are:
- RM48x rev C --> assessment complete; certification expected shortly
- RM46x rev B --> certified as of 11/2014
- RM42x rev A --> assessment starts this week, estimated early 3Q15 completion
The device revisions are planned to go through functional safety assessment in 2015, following certifications of the current silicon revisions.
- RM48x rev D --> estimated 4Q15 completion
- RM46x rev C --> estimated 3Q15 completion
- RM42x rev B --> estimated 4Q15 completion
Impact of the fix
The following table suggests what changes may be required for the new revisions.
|
Errata |
Change required for new revisions |
|
Power-on reset during bank 7 Sector erase may corrupt other sectors (erratum DEVICE#B041) |
May leave workaround in place, no change to SW required |
|
Reads of Bank7 may be corrupted by short glitches on nPORST pin (erratum DEVICE#B042) |
May leave workaround in place, no change to SW required |
|
Incorrect Write to External Memory using Store-Multiple CPU instruction (erratum DEVICE#B064) |
May leave workaround in place, no change to SW required Change can be made to re-gain EMIF performance |
|
CPU write to peripheral or EMIF may be lost (erratum DEVICE#B071) |
May leave workaround in place, no change to SW required |
|
PBIST ROM Algorithm Doesn’t Execute (erratum PBIST#4) |
May leave workaround in place, no change to SW required |
|
Change to PLL Lock Time (erratum SWF021#44) |
Evaluate impact of additional 384 OSCIN cycles |
TI does not anticipate the changes made in revised devices to impact estimated safety metrics in the device safety analysis reports nor recommendations made in device safety manuals. The customer is responsible for evaluating all functional safety related impact, if any, of these changes to the implemented system and to take appropriate actions to mitigate any perceived impact to system level functional safety.
Regards,
Dave
