Cannot clear ESM1 ESMEPSR register when debugging RM57Lx_demo_software project of "Hercules Safety MCU Demos" (4.0.0)

Hi Sunil,

Thank you for your answer to my question!

Based on your suggestions, I first re-ran the program in debugging mode and checked the CcmR5 registers. These registers all have the 0 values and it seemed that all CCM errors were cleared. Still the esmREG ->EPSR value was zero and setting esmREG->EKR = 0x5 didn't bring it to high (esmREG ->EPSR to 0x1). I'm not sure if I have checked the correct CCM registers for errors. I also want to know how to clear the error flags inside the CCM if there is a error happened.

At the same time, I still suspect that the ESM (Error Signaling Module) is not working correctly because the value of the esmREG->LTCR (ESM Low-Time Counter Register) should decrease (count-down) over the time. However, I tried repeatedly breaking into the program over the time and every time it stays at the same initial value 0x3FFF. That indicates that the ESM didn't response to the value changes in the esmREG->EKR register and the error register esmREG ->EPSR would not be reset to high.

Regards,
Ruiming

Hi Sunil,

I have tried to clear these 3 registers as you suggested, it still doesn't work.

The following is the code changes I made in the main() function located in the "Hercules Safety MCU Demos/4.0.0/RM57x_target_sources/HALCoGen/source/HL_sys_main.c" file:

void main(void)
{
/* USER CODE BEGIN (3) */
run_LED_StartUp();
swi_enable_fiq_irq();
sciInit();
sciReceive(sciREG1, 12, receive_command);
hetInit();
adcInit();
gioInit();
esmInit();
{
#include "HL_reg_ccmr5.h"
#include "HL_reg_esm.h"
unsigned int uValue;
uValue = ccmr5REG->CCMSR1;
ccmr5REG->CCMSR1 = (uValue | 0x00010000);
esmREG->SR1[1] = 0x00000001;
esmREG->SSR2 = 0x00000001;
}
esmClearErrPin();
canInit();
...


I also paste the registers contents below which is taken shortly after warm RST by the debugger (at the beginning of the _c_int00(void) function located in the HL_sys_startup.c file):


CcmR5
CcmSr1 0x00000000 CCMR5 Status Register1 [Memory Mapped]
CcmKeyR1 0x00000000 CCMR5 Key Register1 [Memory Mapped]
CcmSr2 0x00000000 CCMR5 Status Register2 [Memory Mapped]
CcmKeyR2 0x00000000 CCMR5 Key Register2 [Memory Mapped]
CcmSr3 0x00000000 CCMR5 Status Register3 [Memory Mapped]
CcmKeyR3 0x00000000 CCMR5 Key Register3 [Memory Mapped]
CcmPolCntrl 0x00000000 CCMR5 Polarity Control Register [Memory Mapped]
CcmSr4 0x00000000 CCMR5 Status Register4 [Memory Mapped]
CcmKeyR4 0x00000000 CCMR5 Key Register4 [Memory Mapped]
CcmPDStat0 0x00000000 CCMR5 Power Domain Status Register0 [Memory Mapped]
CcmPDStat1 0x00000000 CCMR5 Power Domain Status Register1 [Memory Mapped]
Crc1
Crc2
Dcc1
Dcc2
Dma
Dmm
Esm1
IflErrPinSet1 0x00000000 Influence Error Pin Set/Status Register 1 [Memory Mapped]
IflErrPinClr1 0x00000000 Influence Error Pin Clear/Status Register 1 [Memory Mapped]
IntEnaSet1 0x00000000 Interrupt Enable Set/Status Register 1 [Memory Mapped]
IntEnaClr1 0x00000000 Interrupt Enable Clear/Status Register 1 [Memory Mapped]
IntLvlSet1 0x00000000 Interrupt Level Set/Status Register 1 [Memory Mapped]
IntLvlClr1 0x00000000 Interrupt Level Clear/Status Register 1 [Memory Mapped]
Stat1 0x80000000 Status Register 1 [Memory Mapped]
Stat2 0x00000000 Status Register 2 [Memory Mapped]
Stat3 0x00000000 Status Register 3 [Memory Mapped]
ErrPinStat 0x00000000 Error Pin Status Register [Memory Mapped]
IntOffstHgh 0x00000000 Interrupt Offset High Register [Memory Mapped]
IntOffstLow 0x00000000 Interrupt Offset Low Register [Memory Mapped]
LtCnt 0x00003FFF Low-Time Counter Register [Memory Mapped]
LtCntPre 0x00003FFF Low-Time Counter Preload Register [Memory Mapped]
ErrKey 0x00000000 Error Key Register [Memory Mapped]
ShdwStat2 0x00000004 Status Shadow Register [Memory Mapped]
IflErrPinSet4 0x00000000 Influence Error Pin Set/Status Register 4 [Memory Mapped]
IflErrPinClr4 0x00000000 Influence Error Pin Clear/Status Register 4 [Memory Mapped]
IntEnaSet4 0x00000000 Interrupt Enable Set/Status Register 4 [Memory Mapped]
IntEnaClr4 0x00000000 Interrupt Enable Clear/Status Register 4 [Memory Mapped]
IntLvlSet4 0x00000000 Interrupt Level Set/Status Register 4 [Memory Mapped]
IntLvlClr4 0x00000000 Interrupt Level Clear/Status Register 4 [Memory Mapped]
Stat4 0x00000000 Status Register 4 [Memory Mapped]
Stat5 0x00000000 Status Register 5 [Memory Mapped]
Stat6 0x00000000 Status Register 6 [Memory Mapped]
ShdwStat5 0x00000000 Status Shadow Register5 [Memory Mapped]
IflErrPinSet7 0x00000000 Influence Error Pin Set/Status Register 7 [Memory Mapped]
IflErrPinClr7 0x00000000 Influence Error Pin Clear/Status Register 7 [Memory Mapped]
IntEnaSet7 0x00000000 Interrupt Enable Set/Status Register 7 [Memory Mapped]
IntEnaClr7 0x00000000 Interrupt Enable Clear/Status Register 7 [Memory Mapped]
IntLvlSet7 0x00000000 Interrupt Level Set/Status Register 7 [Memory Mapped]
IntLvlClr7 0x00000000 Interrupt Level Clear/Status Register 7 [Memory Mapped]
Stat7 0x04000000 Status Register 7 [Memory Mapped]
Stat8 0x00000000 Status Register 8 [Memory Mapped]
Stat9 0x00000000 Status Register 9 [Memory Mapped]
ShdwStat8 0x00000000 Status Shadow Register8 [Memory Mapped]
IflErrPinSet10 0x00000000 Influence Error Pin Set/Status Register 10 [Memory Mapped]
IflErrPinClr10 0x00000000 Influence Error Pin Clear/Status Register 10 [Memory Mapped]
IntEnaSet10 0x00000000 Interrupt Enable Set/Status Register 10 [Memory Mapped]
IntEnaClr10 0x00000000 Interrupt Enable Clear/Status Register 10 [Memory Mapped]
IntLvlSet10 0x00000000 Interrupt Level Set/Status Register 10 [Memory Mapped]
IntLvlClr10 0x00000000 Interrupt Level Clear/Status Register 10 [Memory Mapped]
Stat10 0x00000000 Status Register 10 [Memory Mapped]
Stat11 0x00000000 Status Register 11 [Memory Mapped]
Stat12 0x00000000 Status Register 12 [Memory Mapped]
ShdwStat11 0x00000000 Status Shadow Register11 [Memory Mapped]


Please note the following registers:
CcmR5:
CcmSr1 = 0x00000000 (and all other CcmR5 registers are all 0s)
Esm1:
Stat1 = 0x80000000
Stat2 = 0x00000000
ShdwStat2 = 0x00000004
Stat7 = 0x04000000 (for some other test runs, this register has the value 0x00000000)

I hope these debug dumps will help you a little bit in figuring out what may cause the problem.

Thanks,

Ruiming

Ruiming,

The CCM compare error is flagged as bit 2 of the ESM group2 status register. So you need to write 0x4 to clear this bit in the esmREG->SR1[1] and esmREG->SSR2 registers.

Regards,
Sunil

Hi Sunil,

I have reviewed more on the RM57x_target_sources project source code, I found that on chip reset (warm nRST or nPORRST), these registers have already been cleared in the function esmInit() which is called in the function _c_int00(). The _c_int00() is the entry-point function called by reset interrupt handler.

I also have found the "RM57Lx Microcontroller Silicon Errata (Silicon Revision A)(Rev. A)" (spnz214a.pdf) document has mentioned the similar issue on page 21. I guess this is a known issue. But the suggested workaround doesn't work in my case. The puzzling problem is that once the ESM ERROR pin is driven low across a warm nRST, we can never clear it by setting the ESMEKR = 0x5. This seems to me is another chip defect which has been reported yet.

I will stop troubleshooting this issue any more and will continue to use the evaluation board without using the ESM module in the development phase.

Thanks again for all your help!

Regards,

Ruiming