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HET IDE and TMS570LC43xx

Other Parts Discussed in Thread: TMS570LS3137

Hello,

I 've downloaded and install HET IDE Release 3.3 (30 Jan 2012) but when I try to create a project the only available devices are TMS570LSnnXXX(PGE|ZWT) with nn=10,20,21,31.

Unfortunately, I use the demo board (HDK) TMS570LC43x.

Do someone know what to do, because I think it is the latest version of HET IDE.

Regards.

Fabrice

  • Hello Fabrice,

    You can choose the LS31x or LS21x devices for your HET code development. These devices include the same version of the N2HET module as that on the LC43x MCUs.

    On our side, we will try to expand the choices of devices available in the HET IDE tool.

    Regards,
    Sunil
  • Fabrice,

    Create a project using the TMS570LS3137.   Once you have a project created - go to the menu Tools->Device Configuration.

    You can save your own device configuration -- save as somethign like:   'my_lc4357'.    Then you can increase the memory size

    and you can change the pin availability & direction.   

  • Hello,

    thank you Sunil and Anthony for your help.

    Now I just try to simulate with HET IDE the skeleton of my code (so I have'nt verify it works on target), but I don't know why I have an overflow error

    and how to do a waiting loop (512µs long).

    See below I give to you the code that I test. It seems that the loop with CNT is very limited, I saw max=4 in the TI's examples.

    So can you explain to me:

    1) how to do a waiting loop

    2) how to avoid overflow error or to investigate such error with HET IDE

    (Code)

    ;INTEG_PERIOD    .equ  39920
    INTEG_PERIOD    .equ  2
    ;ADC_PERIOD      .equ   1597
    ADC_PERIOD      .equ   3
    UNLOCK_KEY    .equ  0xA
    ;.loop 7
    ;ACQ:x::

    ;wait for unlock by CPU
    LOCK   MOV32 { next=BEG_1,remote=DUMMY,type=IMTOREG,reg=T,data=0xA}  ;test version no lock
    ;LOCK   MOV32 { next=BEG_1,remote=DUMMY,type=IMTOREG,reg=T,data=0x5}
    BEG_1  ECMP  { next=LOCK ,cond_addr=BEG_2,reg=T,data=UNLOCK_KEY,pin=0}
    BEG_2  MOV32 { next=STA_1,remote=DUMMY,type=IMTOREG,reg=T,data=0x0}
    ;start integration 2 GPIO to manage (pin 10 and 11)
    STA_1  CNT   { next=STA_2,reg=A,irq=OFF,max=INTEG_PERIOD}
    STA_2  ECMP  { next=STA_3,pin=10,action=SET  ,reg=T,data=0}
    STA_3  ECMP  { next=STA_4,pin=11,action=CLEAR,reg=T,data=0}
    STA_4  BR    { next=STA_1,cond_addr=STO_1,event=Z}
    ;stop integration 2 GPIO to manage (pin 10 and 11)
    STO_1  ECMP  { next=STO_2,pin=10,action=SET,reg=T,data=0}
    STO_2  ECMP  { next=ADC_1,pin=11,action=SET,reg=T,data=0}
    ;ADC event start acquisition
    ADC_1  CNT   { next=ADC_2,reg=A,max=ADC_PERIOD};
    ADC_2  MOV32 { next=ADC_3,remote=DUMMY,type=REMTOREG,reg=A} ; to be modified (generate ADC event)
    ADC_3  BR    { next=ADC_1,cond_addr=DIS_1,event=Z}
    ;discharge integrator 2 GPIO to manage (pin 10 and 11)
    DIS_1  ECMP  { next=DIS_2,pin=10,action=CLEAR,reg=T,data=0}
    DIS_2  ECMP  { next=LOCK ,pin=11,action=SET  ,reg=T,data=0}
    DUMMY  BR    { next=DUMMY,cond_addr=DUMMY,event=NOCOND,irq=OFF}

    Regards,

    Fabrice

  • Hello Fabrice,

     The number of clock cycles to execute your program must be less than one loop resolution period (LRP). I don't know your NHETPFR register setting. If you configure the NHETPFR with 0x700 then it means there are 128 VCLK2 in one LRP. This means you need to make sure your entire program will complete within 128 VCLK2 cycles. The reason you have overflow is of course that you execeed the number of cycles allocated per LRP.

    Looking at your code I see several problems.

    1. In STA_4 the BR will branch back to STA_1 as long the CNT hasn't reached the max value. In your case, you set the max=2 then this means that the NHET will execute STA_1, STA_2, STA_3 and STA_4 three times. This will take 4 * 3 = 12 cycles.

    2. You have the same problem in ADC_3 where you branch back to ADC_1.

    3. In DIS_2 you do not specify the conditional address. By default the assembler will assume the conditional addres to be the next address which is the DUMMY. When the condition is true in DIS_2 it jumps to DUMMY where it will branch to itself forever.

     I understand that NHET will take some learning curve to master. I strongly recommend that you look up some of the NHET app notes and getting started user guide to have a better understanding on NHET programming and architecture.

      In the HET IDE, look under Tools->Algorithm Library you will find quite a few examples on PWM generation. Try to play with these examples first and I hope you will soon get a hang of it.

  • Hello Charles,

    I understand your remarks and suggestions. (I set NHETPFR with 0x700 instead of 0x500).

    To correct the point 3. , I insert a line BR {next=LOCK,cond_addr=LOCK,event=NOLOCK} as for in the "SPNA220–May 2015" example, before the DUMMY instruction.

    With this correction, the simulation is running as long as I want. Does it mean that the return to the first instruction line is considered as the program is complete, as you explained to me at the beginning of your answer? Because I didn't read the definition of this constraint in user manual SPNU490.

    Regards;

    Fabrice

  • Fabrice,

      Yes, returning to the first instruction is considered as the end of the program. With your current fix you may not have a problem. But as soon as you change the CNT max to a larger value then you will run into an overflow again. For example, if you set the CNT max to 100 then you will be looping between STA_1 and STA_4 for 400 cycles and this will immediately overflow.

  • Charles,
    Yes, I known I can't go this way to reach the expected behavior.
    I've found an example in the forum with a big CNT (I try to simulate it but without appropriate stimulus the FOR1 and FOR2 instructions are never reached).
    _e2e.ti.com/.../1112600
    Do you know a pattern to loop a specific time greater than the LR, so to loop with return at the first line ?

    Regards
    Charles
  • Hello Fabrice,

      As I mentioned, you need to ensure that the total number of clock cycles taken to execute the HET program does not exceed one LRP. I'm not sure what you are trying to accomplish in your program. If you want to generate a PWM, there are many ways to do it. Your seem wanting to use the SET and CLEAR action method to control the pin. Below is an example to generate PWM using SET and CLEAR method. You can paste the code into the HET IDE for simulation.

    L00   CNT    {next = 0x01, reg = A, irq = OFF, max = 0x10}
    L01   ECMP   {next = 0x04, hr_lr=HIGH, en_pin_action = ON, cond_addr = 0x02, pin = 0x00, action = SET, reg = A, irq = OFF, data = 0x01, hr_data = 0x1F}
    L02   MOV64  {next = 0x04, remote = 0x01, en_pin_action = on, cond_addr = 0x03, pin = 0x00, comp_mode = ECMP, action = CLEAR,reg = A, irq = off, data = 0x09, hr_data = 0x01}
    L03   MOV64  {next = 0x04, remote = 0x01, en_pin_action = on, cond_addr = 0x02, pin = 0x00, comp_mode = ECMP, action = SET, reg = A, irq = off, data = 0x01, hr_data = 0x1f}
    L04   BR { next=L00,cond_addr=L00,event=NOCOND};

    Another critical point I want to bring out is that you can only have one action on a pin in each LRP. The action will take place synchronized to the beginning of the next LRP. For example,
    if you want to have an action=SET on a pin, then the pin will NOT be set immeidately in the cycle the instruction is executed but rather synchronized to the beginning of the next LRP. So you
    must NOT have multiple actions on a pin in one LRP. Looking at your program I see this problem. In your STA_3 you want to clear pin11 but in STO_2 you want to set pin11. If these
    two instructions are executed in the same LRP, then NHET does not know what you really want. In addition, each pin has the associated high resolution logic where you can specify the
    high resolution delay for the action to take place after synchronizing the action to the next LRP. The NHET will actually ignore the action that you want to create in the second
    instruction (i.e. ignoring STO_2 if you specify the hl_lr=HIGH in the STA_3).